From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Terry Bowman <terry.bowman@amd.com>
Cc: <alison.schofield@intel.com>, <vishal.l.verma@intel.com>,
<ira.weiny@intel.com>, <bwidawsk@kernel.org>,
<dan.j.williams@intel.com>, <dave.jiang@intel.com>,
<linux-cxl@vger.kernel.org>, <rrichter@amd.com>,
<linux-kernel@vger.kernel.org>, <bhelgaas@google.com>
Subject: Re: [PATCH v9 15/15] cxl/core/regs: Rename phys_addr in cxl_map_component_regs()
Date: Tue, 29 Aug 2023 14:54:01 +0100 [thread overview]
Message-ID: <20230829145401.0000554a@Huawei.com> (raw)
In-Reply-To: <20230825233211.3029825-16-terry.bowman@amd.com>
On Fri, 25 Aug 2023 18:32:11 -0500
Terry Bowman <terry.bowman@amd.com> wrote:
> From: Robert Richter <rrichter@amd.com>
>
> Trivial change that renames variable phys_addr in
> cxl_map_component_regs() to shorten its length to keep the 80 char
> size limit for the line and also for consistency between the different
> paths.
>
LGTM
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Signed-off-by: Robert Richter <rrichter@amd.com>
> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> ---
> drivers/cxl/core/regs.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
> index 5cb78b76c757..f8f26fe80489 100644
> --- a/drivers/cxl/core/regs.c
> +++ b/drivers/cxl/core/regs.c
> @@ -217,16 +217,16 @@ int cxl_map_component_regs(const struct cxl_register_map *map,
>
> for (i = 0; i < ARRAY_SIZE(mapinfo); i++) {
> struct mapinfo *mi = &mapinfo[i];
> - resource_size_t phys_addr;
> + resource_size_t addr;
> resource_size_t length;
>
> if (!mi->rmap->valid)
> continue;
> if (!test_bit(mi->rmap->id, &map_mask))
> continue;
> - phys_addr = map->resource + mi->rmap->offset;
> + addr = map->resource + mi->rmap->offset;
> length = mi->rmap->size;
> - *(mi->addr) = devm_cxl_iomap_block(dev, phys_addr, length);
> + *(mi->addr) = devm_cxl_iomap_block(dev, addr, length);
> if (!*(mi->addr))
> return -ENOMEM;
> }
prev parent reply other threads:[~2023-08-29 13:55 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-25 23:31 [PATCH v9 00/15] cxl/pci: Add support for RCH RAS error handling Terry Bowman
2023-08-25 23:31 ` [PATCH v9 01/15] cxl/port: Pre-initialize component register mappings Terry Bowman
2023-08-29 13:38 ` Jonathan Cameron
2023-08-31 12:22 ` Robert Richter
2023-09-01 9:06 ` Jonathan Cameron
2023-08-25 23:31 ` [PATCH v9 02/15] cxl/regs: Prepare for multiple users of " Terry Bowman
2023-08-29 13:52 ` Jonathan Cameron
2023-08-31 12:43 ` Robert Richter
2023-09-01 9:08 ` Jonathan Cameron
2023-08-31 18:11 ` Dan Williams
2023-09-01 9:10 ` Jonathan Cameron
2023-08-25 23:31 ` [PATCH v9 03/15] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state Terry Bowman
2023-08-25 23:32 ` [PATCH v9 04/15] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability Terry Bowman
2023-08-25 23:32 ` [PATCH v9 05/15] cxl/pci: Remove Component Register base address from struct cxl_dev_state Terry Bowman
2023-08-25 23:32 ` [PATCH v9 06/15] cxl/port: Remove Component Register base address from struct cxl_port Terry Bowman
2023-08-25 23:32 ` [PATCH v9 07/15] cxl/pci: Add RCH downstream port AER register discovery Terry Bowman
2023-08-25 23:32 ` [PATCH v9 08/15] PCI/AER: Refactor cper_print_aer() for use by CXL driver module Terry Bowman
2023-08-25 23:32 ` [PATCH v9 09/15] cxl/pci: Update CXL error logging to use RAS register address Terry Bowman
2023-08-25 23:32 ` [PATCH v9 10/15] cxl/pci: Map RCH downstream AER registers for logging protocol errors Terry Bowman
2023-08-25 23:32 ` [PATCH v9 11/15] cxl/pci: Add RCH downstream port error logging Terry Bowman
2023-08-25 23:32 ` [PATCH v9 12/15] cxl/pci: Disable root port interrupts in RCH mode Terry Bowman
2023-08-25 23:32 ` [PATCH v9 13/15] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler Terry Bowman
2023-08-25 23:32 ` [PATCH v9 14/15] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling Terry Bowman
2023-08-25 23:32 ` [PATCH v9 15/15] cxl/core/regs: Rename phys_addr in cxl_map_component_regs() Terry Bowman
2023-08-29 13:54 ` Jonathan Cameron [this message]
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