From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Terry Bowman <terry.bowman@amd.com>
Cc: <alison.schofield@intel.com>, <vishal.l.verma@intel.com>,
<ira.weiny@intel.com>, <bwidawsk@kernel.org>,
<dan.j.williams@intel.com>, <dave.jiang@intel.com>,
<linux-cxl@vger.kernel.org>, <rrichter@amd.com>,
<linux-kernel@vger.kernel.org>, <bhelgaas@google.com>
Subject: Re: [PATCH v10 02/15] cxl/regs: Prepare for multiple users of register mappings
Date: Fri, 1 Sep 2023 10:15:27 +0100 [thread overview]
Message-ID: <20230901101527.000031ba@Huawei.com> (raw)
In-Reply-To: <20230831152031.184295-3-terry.bowman@amd.com>
On Thu, 31 Aug 2023 10:20:18 -0500
Terry Bowman <terry.bowman@amd.com> wrote:
> From: Robert Richter <rrichter@amd.com>
>
> The function devm_cxl_iomap_block() is used to map register mappings
> of CXL component or device registers. A @dev is used to unmap the IO
> regions during device removal.
>
> Now, there are multiple devices using the register mappings. E.g. the
> RAS cap of the Component Registers is used by cxl_pci, the HDM cap
> used in cxl_mem. This could cause IO blocks not being freed and a
> subsequent reinitialization to fail if the same device is used for
> both.
>
> To prevent that, expand cxl_map_component_regs() to pass a @dev to be
> used with devm to IO unmap. This allows to pass the device that
> actually is creating and using the IO region.
>
> For symmetry also change the function i/f of cxl_map_device_regs().
>
> Signed-off-by: Robert Richter <rrichter@amd.com>
> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
I was ambiguous in reply to previous, but my RB not valid here as it
stands. Just replying so that doesn't get lost for v11!
> ---
> drivers/cxl/core/hdm.c | 3 ++-
> drivers/cxl/core/regs.c | 4 ++--
> drivers/cxl/cxl.h | 2 ++
> drivers/cxl/pci.c | 4 ++--
> 4 files changed, 8 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
> index 4449b34a80cc..17c8ba8c75e0 100644
> --- a/drivers/cxl/core/hdm.c
> +++ b/drivers/cxl/core/hdm.c
> @@ -98,7 +98,8 @@ static int map_hdm_decoder_regs(struct cxl_port *port, void __iomem *crb,
> return -ENODEV;
> }
>
> - return cxl_map_component_regs(&map, regs, BIT(CXL_CM_CAP_CAP_ID_HDM));
> + return cxl_map_component_regs(&map, &port->dev, regs,
> + BIT(CXL_CM_CAP_CAP_ID_HDM));
> }
>
> static bool should_emulate_decoders(struct cxl_endpoint_dvsec_info *info)
> diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
> index 6281127b3e9d..dfc3e272e7d8 100644
> --- a/drivers/cxl/core/regs.c
> +++ b/drivers/cxl/core/regs.c
> @@ -201,10 +201,10 @@ void __iomem *devm_cxl_iomap_block(struct device *dev, resource_size_t addr,
> }
>
> int cxl_map_component_regs(const struct cxl_register_map *map,
> + struct device *dev,
> struct cxl_component_regs *regs,
> unsigned long map_mask)
> {
> - struct device *dev = map->dev;
> struct mapinfo {
> const struct cxl_reg_map *rmap;
> void __iomem **addr;
> @@ -235,9 +235,9 @@ int cxl_map_component_regs(const struct cxl_register_map *map,
> EXPORT_SYMBOL_NS_GPL(cxl_map_component_regs, CXL);
>
> int cxl_map_device_regs(const struct cxl_register_map *map,
> + struct device *dev,
> struct cxl_device_regs *regs)
> {
> - struct device *dev = map->dev;
> resource_size_t phys_addr = map->resource;
> struct mapinfo {
> const struct cxl_reg_map *rmap;
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index 76d92561af29..ec8ba9ebcf64 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -274,9 +274,11 @@ void cxl_probe_component_regs(struct device *dev, void __iomem *base,
> void cxl_probe_device_regs(struct device *dev, void __iomem *base,
> struct cxl_device_reg_map *map);
> int cxl_map_component_regs(const struct cxl_register_map *map,
> + struct device *dev,
> struct cxl_component_regs *regs,
> unsigned long map_mask);
> int cxl_map_device_regs(const struct cxl_register_map *map,
> + struct device *dev,
> struct cxl_device_regs *regs);
> int cxl_map_pmu_regs(struct pci_dev *pdev, struct cxl_pmu_regs *regs,
> struct cxl_register_map *map);
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index 48f88d96029d..88ddcff8a0b2 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
> @@ -827,7 +827,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
> if (rc)
> return rc;
>
> - rc = cxl_map_device_regs(&map, &cxlds->regs.device_regs);
> + rc = cxl_map_device_regs(&map, cxlds->dev, &cxlds->regs.device_regs);
> if (rc)
> return rc;
>
> @@ -844,7 +844,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
>
> cxlds->component_reg_phys = map.resource;
>
> - rc = cxl_map_component_regs(&map, &cxlds->regs.component,
> + rc = cxl_map_component_regs(&map, cxlds->dev, &cxlds->regs.component,
> BIT(CXL_CM_CAP_CAP_ID_RAS));
> if (rc)
> dev_dbg(&pdev->dev, "Failed to map RAS capability.\n");
next prev parent reply other threads:[~2023-09-01 9:15 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-31 15:20 [PATCH v10 00/15] cxl/pci: Add support for RCH RAS error handling Terry Bowman
2023-08-31 15:20 ` [PATCH v10 01/15] cxl/port: Pre-initialize component register mappings Terry Bowman
2023-08-31 15:20 ` [PATCH v10 02/15] cxl/regs: Prepare for multiple users of " Terry Bowman
2023-09-01 9:15 ` Jonathan Cameron [this message]
2023-09-02 13:54 ` Robert Richter
2023-08-31 15:20 ` [PATCH v10 03/15] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state Terry Bowman
2023-08-31 15:20 ` [PATCH v10 04/15] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability Terry Bowman
2023-08-31 18:34 ` Dan Williams
2023-09-15 0:15 ` Dan Williams
2023-09-15 21:53 ` Robert Richter
2023-09-15 22:54 ` Dan Williams
2023-08-31 15:20 ` [PATCH v10 05/15] cxl/pci: Remove Component Register base address from struct cxl_dev_state Terry Bowman
2023-08-31 15:20 ` [PATCH v10 06/15] cxl/port: Remove Component Register base address from struct cxl_port Terry Bowman
2023-08-31 15:20 ` [PATCH v10 07/15] cxl/pci: Add RCH downstream port AER register discovery Terry Bowman
2023-08-31 18:51 ` Dan Williams
2023-09-05 16:55 ` Terry Bowman
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