* [PATCH] perf: CXL: fix mismatched number of counters mask [not found] <CGME20230905123044epcas2p2b1052956527cf63a03e2895d4b93e7e1@epcas2p2.samsung.com> @ 2023-09-05 12:33 ` Jeongtae Park 2023-09-05 14:28 ` Will Deacon 2023-09-05 16:01 ` Will Deacon 0 siblings, 2 replies; 5+ messages in thread From: Jeongtae Park @ 2023-09-05 12:33 UTC (permalink / raw) To: linux-cxl, Jonathan Cameron Cc: linux-arm-kernel, linux-kernel, Will Deacon, Mark Rutland, Kyungsan Kim, Wonjae Lee, Hojin Nam, Junhyeok Im, Jehoon Park, Jeongtae Park The number of Count Units field is described as 6 bits long in the CXL 3.0 specification. However, its mask value was only declared as 5 bits long. Signed-off-by: Jeongtae Park <jtp.park@samsung.com> --- drivers/perf/cxl_pmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/perf/cxl_pmu.c b/drivers/perf/cxl_pmu.c index 0a8f597e695b..365d964b0f6a 100644 --- a/drivers/perf/cxl_pmu.c +++ b/drivers/perf/cxl_pmu.c @@ -25,7 +25,7 @@ #include "../cxl/pmu.h" #define CXL_PMU_CAP_REG 0x0 -#define CXL_PMU_CAP_NUM_COUNTERS_MSK GENMASK_ULL(4, 0) +#define CXL_PMU_CAP_NUM_COUNTERS_MSK GENMASK_ULL(5, 0) #define CXL_PMU_CAP_COUNTER_WIDTH_MSK GENMASK_ULL(15, 8) #define CXL_PMU_CAP_NUM_EVN_CAP_REG_SUP_MSK GENMASK_ULL(24, 20) #define CXL_PMU_CAP_FILTERS_SUP_MSK GENMASK_ULL(39, 32) base-commit: fe77cc2e5a6a7c85f5c6ef8a39d7694ffc7f41c9 -- 2.34.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH] perf: CXL: fix mismatched number of counters mask 2023-09-05 12:33 ` [PATCH] perf: CXL: fix mismatched number of counters mask Jeongtae Park @ 2023-09-05 14:28 ` Will Deacon 2023-09-05 14:46 ` Jonathan Cameron 2023-09-05 16:01 ` Will Deacon 1 sibling, 1 reply; 5+ messages in thread From: Will Deacon @ 2023-09-05 14:28 UTC (permalink / raw) To: Jeongtae Park Cc: linux-cxl, Jonathan Cameron, linux-arm-kernel, linux-kernel, Mark Rutland, Kyungsan Kim, Wonjae Lee, Hojin Nam, Junhyeok Im, Jehoon Park On Tue, Sep 05, 2023 at 09:33:09PM +0900, Jeongtae Park wrote: > The number of Count Units field is described as 6 bits long > in the CXL 3.0 specification. However, its mask value was > only declared as 5 bits long. > > Signed-off-by: Jeongtae Park <jtp.park@samsung.com> > --- > drivers/perf/cxl_pmu.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/perf/cxl_pmu.c b/drivers/perf/cxl_pmu.c > index 0a8f597e695b..365d964b0f6a 100644 > --- a/drivers/perf/cxl_pmu.c > +++ b/drivers/perf/cxl_pmu.c > @@ -25,7 +25,7 @@ > #include "../cxl/pmu.h" > > #define CXL_PMU_CAP_REG 0x0 > -#define CXL_PMU_CAP_NUM_COUNTERS_MSK GENMASK_ULL(4, 0) > +#define CXL_PMU_CAP_NUM_COUNTERS_MSK GENMASK_ULL(5, 0) > #define CXL_PMU_CAP_COUNTER_WIDTH_MSK GENMASK_ULL(15, 8) > #define CXL_PMU_CAP_NUM_EVN_CAP_REG_SUP_MSK GENMASK_ULL(24, 20) > #define CXL_PMU_CAP_FILTERS_SUP_MSK GENMASK_ULL(39, 32) I don't have access to the CXL spec, but widening this mask looks like it puts us out-of-whack with CXL_PMU_MAX_COUNTERS. Did v3.0 of the spec bump the number of counters? If so, can you please check that this is a backwards-compatible change? Will ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] perf: CXL: fix mismatched number of counters mask 2023-09-05 14:28 ` Will Deacon @ 2023-09-05 14:46 ` Jonathan Cameron 2023-09-05 14:51 ` Will Deacon 0 siblings, 1 reply; 5+ messages in thread From: Jonathan Cameron @ 2023-09-05 14:46 UTC (permalink / raw) To: Will Deacon Cc: Jeongtae Park, linux-cxl, linux-arm-kernel, linux-kernel, Mark Rutland, Kyungsan Kim, Wonjae Lee, Hojin Nam, Junhyeok Im, Jehoon Park On Tue, 5 Sep 2023 15:28:54 +0100 Will Deacon <will@kernel.org> wrote: > On Tue, Sep 05, 2023 at 09:33:09PM +0900, Jeongtae Park wrote: > > The number of Count Units field is described as 6 bits long > > in the CXL 3.0 specification. However, its mask value was > > only declared as 5 bits long. > > > > Signed-off-by: Jeongtae Park <jtp.park@samsung.com> > > --- > > drivers/perf/cxl_pmu.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/perf/cxl_pmu.c b/drivers/perf/cxl_pmu.c > > index 0a8f597e695b..365d964b0f6a 100644 > > --- a/drivers/perf/cxl_pmu.c > > +++ b/drivers/perf/cxl_pmu.c > > @@ -25,7 +25,7 @@ > > #include "../cxl/pmu.h" > > > > #define CXL_PMU_CAP_REG 0x0 > > -#define CXL_PMU_CAP_NUM_COUNTERS_MSK GENMASK_ULL(4, 0) > > +#define CXL_PMU_CAP_NUM_COUNTERS_MSK GENMASK_ULL(5, 0) > > #define CXL_PMU_CAP_COUNTER_WIDTH_MSK GENMASK_ULL(15, 8) > > #define CXL_PMU_CAP_NUM_EVN_CAP_REG_SUP_MSK GENMASK_ULL(24, 20) > > #define CXL_PMU_CAP_FILTERS_SUP_MSK GENMASK_ULL(39, 32) > > I don't have access to the CXL spec, but widening this mask looks like > it puts us out-of-whack with CXL_PMU_MAX_COUNTERS. > > Did v3.0 of the spec bump the number of counters? If so, can you please > check that this is a backwards-compatible change? CXL Performance monitors were only introduced in CXL 3.0 so not that. The max value that register can take is 0x3f (0 based, so 64 counters == CXL_PMU_MAX_COUNTERS) So it should be 6 bits wide. I did some history digging and this isn't even a draft spec / final spec issue - simple typo I guess. Fix seems correct to me. Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > > Will ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] perf: CXL: fix mismatched number of counters mask 2023-09-05 14:46 ` Jonathan Cameron @ 2023-09-05 14:51 ` Will Deacon 0 siblings, 0 replies; 5+ messages in thread From: Will Deacon @ 2023-09-05 14:51 UTC (permalink / raw) To: Jonathan Cameron Cc: Jeongtae Park, linux-cxl, linux-arm-kernel, linux-kernel, Mark Rutland, Kyungsan Kim, Wonjae Lee, Hojin Nam, Junhyeok Im, Jehoon Park On Tue, Sep 05, 2023 at 03:46:34PM +0100, Jonathan Cameron wrote: > On Tue, 5 Sep 2023 15:28:54 +0100 > Will Deacon <will@kernel.org> wrote: > > > On Tue, Sep 05, 2023 at 09:33:09PM +0900, Jeongtae Park wrote: > > > The number of Count Units field is described as 6 bits long > > > in the CXL 3.0 specification. However, its mask value was > > > only declared as 5 bits long. > > > > > > Signed-off-by: Jeongtae Park <jtp.park@samsung.com> > > > --- > > > drivers/perf/cxl_pmu.c | 2 +- > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > diff --git a/drivers/perf/cxl_pmu.c b/drivers/perf/cxl_pmu.c > > > index 0a8f597e695b..365d964b0f6a 100644 > > > --- a/drivers/perf/cxl_pmu.c > > > +++ b/drivers/perf/cxl_pmu.c > > > @@ -25,7 +25,7 @@ > > > #include "../cxl/pmu.h" > > > > > > #define CXL_PMU_CAP_REG 0x0 > > > -#define CXL_PMU_CAP_NUM_COUNTERS_MSK GENMASK_ULL(4, 0) > > > +#define CXL_PMU_CAP_NUM_COUNTERS_MSK GENMASK_ULL(5, 0) > > > #define CXL_PMU_CAP_COUNTER_WIDTH_MSK GENMASK_ULL(15, 8) > > > #define CXL_PMU_CAP_NUM_EVN_CAP_REG_SUP_MSK GENMASK_ULL(24, 20) > > > #define CXL_PMU_CAP_FILTERS_SUP_MSK GENMASK_ULL(39, 32) > > > > I don't have access to the CXL spec, but widening this mask looks like > > it puts us out-of-whack with CXL_PMU_MAX_COUNTERS. > > > > Did v3.0 of the spec bump the number of counters? If so, can you please > > check that this is a backwards-compatible change? > > CXL Performance monitors were only introduced in CXL 3.0 so not that. Thanks for the information! > The max value that register can take is 0x3f (0 based, so 64 counters == > CXL_PMU_MAX_COUNTERS) > So it should be 6 bits wide. I did some history digging and this isn't > even a draft spec / final spec issue - simple typo I guess. Heh, I blame the heat as I thought this was extending to 7 bits for some reason. Sorry about that. > Fix seems correct to me. > > Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> I'll pick it up, thanks again! Will ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] perf: CXL: fix mismatched number of counters mask 2023-09-05 12:33 ` [PATCH] perf: CXL: fix mismatched number of counters mask Jeongtae Park 2023-09-05 14:28 ` Will Deacon @ 2023-09-05 16:01 ` Will Deacon 1 sibling, 0 replies; 5+ messages in thread From: Will Deacon @ 2023-09-05 16:01 UTC (permalink / raw) To: linux-cxl, Jeongtae Park, Jonathan Cameron Cc: catalin.marinas, kernel-team, Will Deacon, Wonjae Lee, Mark Rutland, Kyungsan Kim, Junhyeok Im, Jehoon Park, Hojin Nam, linux-kernel, linux-arm-kernel On Tue, 5 Sep 2023 21:33:09 +0900, Jeongtae Park wrote: > The number of Count Units field is described as 6 bits long > in the CXL 3.0 specification. However, its mask value was > only declared as 5 bits long. > > Applied to arm64 (for-next/fixes), thanks! [1/1] perf: CXL: fix mismatched number of counters mask https://git.kernel.org/arm64/c/7625df9f4b25 Cheers, -- Will https://fixes.arm64.dev https://next.arm64.dev https://will.arm64.dev ^ permalink raw reply [flat|nested] 5+ messages in thread
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[not found] <CGME20230905123044epcas2p2b1052956527cf63a03e2895d4b93e7e1@epcas2p2.samsung.com>
2023-09-05 12:33 ` [PATCH] perf: CXL: fix mismatched number of counters mask Jeongtae Park
2023-09-05 14:28 ` Will Deacon
2023-09-05 14:46 ` Jonathan Cameron
2023-09-05 14:51 ` Will Deacon
2023-09-05 16:01 ` Will Deacon
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