[PATCH 2/2] arm: dts: am3517-evm: Enable Ethernet PHY Interrupt

Adam Ford
2023-09-07T01:02:23Z

The Ethernet PHY interrupt pin is routed to GPIO_58. Create a
PHY node to configure this GPIO for the interrupt to avoid polling.

Signed-off-by: Adam Ford <aford173@gmail.com>

diff --git a/arch/arm/boot/dts/ti/omap/am3517-evm.dts b/arch/arm/boot/dts/ti/omap/am3517-evm.dts
index 738189ddc8d5..19869ef906a8 100644
--- a/arch/arm/boot/dts/ti/omap/am3517-evm.dts
+++ b/arch/arm/boot/dts/ti/omap/am3517-evm.dts
@@ -172,11 +172,24 @@ hsusb1_phy: hsusb1_phy {
&davinci_emac {
pinctrl-names = "default";
pinctrl-0 = <&ethernet_pins>;
+ phy-mode = "rmii";
+ phy-handle = <&ethphy0>;
status = "okay";
};

&davinci_mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "okay";
+
+ ethphy0: ethernet-phy@0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&enet_phy_pins>;
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <26 IRQ_TYPE_LEVEL_LOW>; /* gpio_58 */
+ };
};

&dss {
@@ -257,6 +270,12 @@ OMAP3_CORE1_IOPAD(0x2210, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_50mhz_clk */
>;
};

+ enet_phy_pins: pinmux_ent_phy_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x20bc, PIN_INPUT | MUX_MODE4) /* gpmc_ncs7.gpio_57 */
+ >;
+ };
+
i2c2_pins: i2c2-pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */
--
2.39.2