From: Anup Patel <apatel@ventanamicro.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Thomas Gleixner <tglx@linutronix.de>,
Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Frank Rowand <frowand.list@gmail.com>,
Conor Dooley <conor+dt@kernel.org>
Cc: Atish Patra <atishp@atishpatra.org>,
Andrew Jones <ajones@ventanamicro.com>,
Sunil V L <sunilvl@ventanamicro.com>,
Saravana Kannan <saravanak@google.com>,
Anup Patel <anup@brainfault.org>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, Anup Patel <apatel@ventanamicro.com>
Subject: [PATCH v8 16/16] MAINTAINERS: Add entry for RISC-V AIA drivers
Date: Tue, 12 Sep 2023 23:19:28 +0530 [thread overview]
Message-ID: <20230912174928.528414-17-apatel@ventanamicro.com> (raw)
In-Reply-To: <20230912174928.528414-1-apatel@ventanamicro.com>
Add myself as maintainer for RISC-V AIA drivers including the
RISC-V INTC driver which supports both AIA and non-AIA platforms.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
MAINTAINERS | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 90f13281d297..6f331ac31d27 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -18410,6 +18410,20 @@ S: Maintained
F: drivers/mtd/nand/raw/r852.c
F: drivers/mtd/nand/raw/r852.h
+RISC-V AIA DRIVERS
+M: Anup Patel <anup@brainfault.org>
+L: linux-riscv@lists.infradead.org
+S: Maintained
+F: Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml
+F: Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml
+F: drivers/irqchip/irq-riscv-aplic-*.c
+F: drivers/irqchip/irq-riscv-aplic-*.h
+F: drivers/irqchip/irq-riscv-imsic-*.c
+F: drivers/irqchip/irq-riscv-imsic-*.h
+F: drivers/irqchip/irq-riscv-intc.c
+F: include/linux/irqchip/riscv-aplic.h
+F: include/linux/irqchip/riscv-imsic.h
+
RISC-V ARCHITECTURE
M: Paul Walmsley <paul.walmsley@sifive.com>
M: Palmer Dabbelt <palmer@dabbelt.com>
--
2.34.1
prev parent reply other threads:[~2023-09-12 17:52 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-12 17:49 [PATCH v8 00/16] Linux RISC-V AIA Support Anup Patel
2023-09-12 17:49 ` [PATCH v8 01/16] RISC-V: Don't fail in riscv_of_parent_hartid() for disabled HARTs Anup Patel
2023-09-20 0:11 ` Atish Patra
2023-09-12 17:49 ` [PATCH v8 02/16] RISC-V: Add riscv_get_intc_hartid() function Anup Patel
2023-09-20 0:19 ` Atish Patra
2023-09-25 7:38 ` Sunil V L
2023-09-26 12:27 ` Anup Patel
2023-09-12 17:49 ` [PATCH v8 03/16] of: property: Add fw_devlink support for msi-parent Anup Patel
2023-09-12 23:00 ` Saravana Kannan
2023-09-13 10:58 ` Anup Patel
2023-09-12 17:49 ` [PATCH v8 04/16] drivers: irqchip/riscv-intc: Mark all INTC nodes as initialized Anup Patel
2023-09-12 17:49 ` [PATCH v8 05/16] irqchip/sifive-plic: Fix syscore registration for multi-socket systems Anup Patel
2023-09-12 17:49 ` [PATCH v8 06/16] irqchip/sifive-plic: Convert PLIC driver into a platform driver Anup Patel
2023-09-12 17:49 ` [PATCH v8 07/16] irqchip/riscv-intc: Add support for RISC-V AIA Anup Patel
2023-09-12 17:49 ` [PATCH v8 08/16] dt-bindings: interrupt-controller: Add RISC-V incoming MSI controller Anup Patel
2023-09-12 17:49 ` [PATCH v8 09/16] irqchip: Add RISC-V incoming MSI controller early driver Anup Patel
2023-09-13 10:33 ` Emil Renner Berthing
2023-09-13 10:57 ` Anup Patel
2023-09-25 7:49 ` Sunil V L
2023-09-27 10:53 ` Anup Patel
2023-09-12 17:49 ` [PATCH v8 10/16] irqchip/riscv-imsic: Add support for platform MSI irqdomain Anup Patel
2023-09-25 13:01 ` Ruan Jinjie
2023-09-25 13:08 ` Anup Patel
2023-09-12 17:49 ` [PATCH v8 11/16] irqchip/riscv-imsic: Add support for PCI " Anup Patel
2023-09-12 17:49 ` [PATCH v8 12/16] dt-bindings: interrupt-controller: Add RISC-V advanced PLIC Anup Patel
2023-09-12 17:49 ` [PATCH v8 13/16] irqchip: Add RISC-V advanced PLIC driver for direct-mode Anup Patel
2023-09-25 7:56 ` Sunil V L
2023-09-25 8:00 ` Sunil V L
2023-09-28 4:38 ` Anup Patel
2023-09-12 17:49 ` [PATCH v8 14/16] irqchip/riscv-aplic: Add support for MSI-mode Anup Patel
2023-09-12 17:49 ` [PATCH v8 15/16] RISC-V: Select APLIC and IMSIC drivers Anup Patel
2023-09-12 17:49 ` Anup Patel [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230912174928.528414-17-apatel@ventanamicro.com \
--to=apatel@ventanamicro.com \
--cc=ajones@ventanamicro.com \
--cc=anup@brainfault.org \
--cc=atishp@atishpatra.org \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=frowand.list@gmail.com \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=maz@kernel.org \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=robh+dt@kernel.org \
--cc=saravanak@google.com \
--cc=sunilvl@ventanamicro.com \
--cc=tglx@linutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox