From: Anup Patel <apatel@ventanamicro.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Thomas Gleixner <tglx@linutronix.de>,
Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Frank Rowand <frowand.list@gmail.com>,
Conor Dooley <conor+dt@kernel.org>
Cc: Atish Patra <atishp@atishpatra.org>,
Andrew Jones <ajones@ventanamicro.com>,
Sunil V L <sunilvl@ventanamicro.com>,
Saravana Kannan <saravanak@google.com>,
Anup Patel <anup@brainfault.org>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, Anup Patel <apatel@ventanamicro.com>
Subject: [PATCH v8 02/16] RISC-V: Add riscv_get_intc_hartid() function
Date: Tue, 12 Sep 2023 23:19:14 +0530 [thread overview]
Message-ID: <20230912174928.528414-3-apatel@ventanamicro.com> (raw)
In-Reply-To: <20230912174928.528414-1-apatel@ventanamicro.com>
We add a common riscv_get_intc_hartid() which help device drivers to
get hartid of the HART associated with a INTC (i.e. local interrupt
controller) fwnode. This new function is more generic compared to
the existing riscv_of_parent_hartid() function hence we also replace
use of riscv_of_parent_hartid() with riscv_get_intc_hartid().
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
arch/riscv/include/asm/processor.h | 4 +++-
arch/riscv/kernel/cpu.c | 13 ++++++++++++-
drivers/irqchip/irq-riscv-intc.c | 2 +-
drivers/irqchip/irq-sifive-plic.c | 3 ++-
4 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h
index 3e23e1786d05..3ce64b3bea4e 100644
--- a/arch/riscv/include/asm/processor.h
+++ b/arch/riscv/include/asm/processor.h
@@ -119,7 +119,9 @@ static inline void wait_for_interrupt(void)
struct device_node;
int riscv_of_processor_hartid(struct device_node *node, unsigned long *hartid);
int riscv_early_of_processor_hartid(struct device_node *node, unsigned long *hartid);
-int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid);
+
+struct fwnode_handle;
+int riscv_get_intc_hartid(struct fwnode_handle *node, unsigned long *hartid);
extern void riscv_fill_hwcap(void);
extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src);
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index 157ace8b262c..ee583eac3c5b 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -123,7 +123,8 @@ int __init riscv_early_of_processor_hartid(struct device_node *node, unsigned lo
* To achieve this, we walk up the DT tree until we find an active
* RISC-V core (HART) node and extract the cpuid from it.
*/
-int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid)
+static int riscv_of_parent_hartid(struct device_node *node,
+ unsigned long *hartid)
{
for (; node; node = node->parent) {
if (of_device_is_compatible(node, "riscv")) {
@@ -139,6 +140,16 @@ int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid)
return -1;
}
+/* Find hart ID of the INTC fwnode. */
+int riscv_get_intc_hartid(struct fwnode_handle *node, unsigned long *hartid)
+{
+ /* Extend this function ACPI in the future. */
+ if (!is_of_node(node))
+ return -ENODEV;
+
+ return riscv_of_parent_hartid(to_of_node(node), hartid);
+}
+
DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
unsigned long riscv_cached_mvendorid(unsigned int cpu_id)
diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
index 4adeee1bc391..65f4a2afb381 100644
--- a/drivers/irqchip/irq-riscv-intc.c
+++ b/drivers/irqchip/irq-riscv-intc.c
@@ -143,7 +143,7 @@ static int __init riscv_intc_init(struct device_node *node,
int rc;
unsigned long hartid;
- rc = riscv_of_parent_hartid(node, &hartid);
+ rc = riscv_get_intc_hartid(of_fwnode_handle(node), &hartid);
if (rc < 0) {
pr_warn("unable to find hart id for %pOF\n", node);
return 0;
diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
index e1484905b7bd..56b0544b1f27 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -477,7 +477,8 @@ static int __init __plic_init(struct device_node *node,
continue;
}
- error = riscv_of_parent_hartid(parent.np, &hartid);
+ error = riscv_get_intc_hartid(of_fwnode_handle(parent.np),
+ &hartid);
if (error < 0) {
pr_warn("failed to parse hart ID for context %d.\n", i);
continue;
--
2.34.1
next prev parent reply other threads:[~2023-09-12 17:50 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-12 17:49 [PATCH v8 00/16] Linux RISC-V AIA Support Anup Patel
2023-09-12 17:49 ` [PATCH v8 01/16] RISC-V: Don't fail in riscv_of_parent_hartid() for disabled HARTs Anup Patel
2023-09-20 0:11 ` Atish Patra
2023-09-12 17:49 ` Anup Patel [this message]
2023-09-20 0:19 ` [PATCH v8 02/16] RISC-V: Add riscv_get_intc_hartid() function Atish Patra
2023-09-25 7:38 ` Sunil V L
2023-09-26 12:27 ` Anup Patel
2023-09-12 17:49 ` [PATCH v8 03/16] of: property: Add fw_devlink support for msi-parent Anup Patel
2023-09-12 23:00 ` Saravana Kannan
2023-09-13 10:58 ` Anup Patel
2023-09-12 17:49 ` [PATCH v8 04/16] drivers: irqchip/riscv-intc: Mark all INTC nodes as initialized Anup Patel
2023-09-12 17:49 ` [PATCH v8 05/16] irqchip/sifive-plic: Fix syscore registration for multi-socket systems Anup Patel
2023-09-12 17:49 ` [PATCH v8 06/16] irqchip/sifive-plic: Convert PLIC driver into a platform driver Anup Patel
2023-09-12 17:49 ` [PATCH v8 07/16] irqchip/riscv-intc: Add support for RISC-V AIA Anup Patel
2023-09-12 17:49 ` [PATCH v8 08/16] dt-bindings: interrupt-controller: Add RISC-V incoming MSI controller Anup Patel
2023-09-12 17:49 ` [PATCH v8 09/16] irqchip: Add RISC-V incoming MSI controller early driver Anup Patel
2023-09-13 10:33 ` Emil Renner Berthing
2023-09-13 10:57 ` Anup Patel
2023-09-25 7:49 ` Sunil V L
2023-09-27 10:53 ` Anup Patel
2023-09-12 17:49 ` [PATCH v8 10/16] irqchip/riscv-imsic: Add support for platform MSI irqdomain Anup Patel
2023-09-25 13:01 ` Ruan Jinjie
2023-09-25 13:08 ` Anup Patel
2023-09-12 17:49 ` [PATCH v8 11/16] irqchip/riscv-imsic: Add support for PCI " Anup Patel
2023-09-12 17:49 ` [PATCH v8 12/16] dt-bindings: interrupt-controller: Add RISC-V advanced PLIC Anup Patel
2023-09-12 17:49 ` [PATCH v8 13/16] irqchip: Add RISC-V advanced PLIC driver for direct-mode Anup Patel
2023-09-25 7:56 ` Sunil V L
2023-09-25 8:00 ` Sunil V L
2023-09-28 4:38 ` Anup Patel
2023-09-12 17:49 ` [PATCH v8 14/16] irqchip/riscv-aplic: Add support for MSI-mode Anup Patel
2023-09-12 17:49 ` [PATCH v8 15/16] RISC-V: Select APLIC and IMSIC drivers Anup Patel
2023-09-12 17:49 ` [PATCH v8 16/16] MAINTAINERS: Add entry for RISC-V AIA drivers Anup Patel
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230912174928.528414-3-apatel@ventanamicro.com \
--to=apatel@ventanamicro.com \
--cc=ajones@ventanamicro.com \
--cc=anup@brainfault.org \
--cc=atishp@atishpatra.org \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=frowand.list@gmail.com \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=maz@kernel.org \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=robh+dt@kernel.org \
--cc=saravanak@google.com \
--cc=sunilvl@ventanamicro.com \
--cc=tglx@linutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox