From: Anup Patel <apatel@ventanamicro.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Thomas Gleixner <tglx@linutronix.de>,
Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Frank Rowand <frowand.list@gmail.com>,
Conor Dooley <conor+dt@kernel.org>
Cc: Atish Patra <atishp@atishpatra.org>,
Andrew Jones <ajones@ventanamicro.com>,
Sunil V L <sunilvl@ventanamicro.com>,
Saravana Kannan <saravanak@google.com>,
Anup Patel <anup@brainfault.org>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, Anup Patel <apatel@ventanamicro.com>
Subject: [PATCH v8 05/16] irqchip/sifive-plic: Fix syscore registration for multi-socket systems
Date: Tue, 12 Sep 2023 23:19:17 +0530 [thread overview]
Message-ID: <20230912174928.528414-6-apatel@ventanamicro.com> (raw)
In-Reply-To: <20230912174928.528414-1-apatel@ventanamicro.com>
On multi-socket systems, we will have a separate PLIC in each socket
so we should register syscore operation only once for multi-socket
systems.
Fixes: e80f0b6a2cf3 ("irqchip/irq-sifive-plic: Add syscore callbacks for hibernation")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
drivers/irqchip/irq-sifive-plic.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
index 56b0544b1f27..62ba27553cc3 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -533,17 +533,18 @@ static int __init __plic_init(struct device_node *node,
}
/*
- * We can have multiple PLIC instances so setup cpuhp state only
- * when context handler for current/boot CPU is present.
+ * We can have multiple PLIC instances so setup cpuhp state
+ * and register syscore operations only when context handler
+ * for current/boot CPU is present.
*/
handler = this_cpu_ptr(&plic_handlers);
if (handler->present && !plic_cpuhp_setup_done) {
cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING,
"irqchip/sifive/plic:starting",
plic_starting_cpu, plic_dying_cpu);
+ register_syscore_ops(&plic_irq_syscore_ops);
plic_cpuhp_setup_done = true;
}
- register_syscore_ops(&plic_irq_syscore_ops);
pr_info("%pOFP: mapped %d interrupts with %d handlers for"
" %d contexts.\n", node, nr_irqs, nr_handlers, nr_contexts);
--
2.34.1
next prev parent reply other threads:[~2023-09-12 17:50 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-12 17:49 [PATCH v8 00/16] Linux RISC-V AIA Support Anup Patel
2023-09-12 17:49 ` [PATCH v8 01/16] RISC-V: Don't fail in riscv_of_parent_hartid() for disabled HARTs Anup Patel
2023-09-20 0:11 ` Atish Patra
2023-09-12 17:49 ` [PATCH v8 02/16] RISC-V: Add riscv_get_intc_hartid() function Anup Patel
2023-09-20 0:19 ` Atish Patra
2023-09-25 7:38 ` Sunil V L
2023-09-26 12:27 ` Anup Patel
2023-09-12 17:49 ` [PATCH v8 03/16] of: property: Add fw_devlink support for msi-parent Anup Patel
2023-09-12 23:00 ` Saravana Kannan
2023-09-13 10:58 ` Anup Patel
2023-09-12 17:49 ` [PATCH v8 04/16] drivers: irqchip/riscv-intc: Mark all INTC nodes as initialized Anup Patel
2023-09-12 17:49 ` Anup Patel [this message]
2023-09-12 17:49 ` [PATCH v8 06/16] irqchip/sifive-plic: Convert PLIC driver into a platform driver Anup Patel
2023-09-12 17:49 ` [PATCH v8 07/16] irqchip/riscv-intc: Add support for RISC-V AIA Anup Patel
2023-09-12 17:49 ` [PATCH v8 08/16] dt-bindings: interrupt-controller: Add RISC-V incoming MSI controller Anup Patel
2023-09-12 17:49 ` [PATCH v8 09/16] irqchip: Add RISC-V incoming MSI controller early driver Anup Patel
2023-09-13 10:33 ` Emil Renner Berthing
2023-09-13 10:57 ` Anup Patel
2023-09-25 7:49 ` Sunil V L
2023-09-27 10:53 ` Anup Patel
2023-09-12 17:49 ` [PATCH v8 10/16] irqchip/riscv-imsic: Add support for platform MSI irqdomain Anup Patel
2023-09-25 13:01 ` Ruan Jinjie
2023-09-25 13:08 ` Anup Patel
2023-09-12 17:49 ` [PATCH v8 11/16] irqchip/riscv-imsic: Add support for PCI " Anup Patel
2023-09-12 17:49 ` [PATCH v8 12/16] dt-bindings: interrupt-controller: Add RISC-V advanced PLIC Anup Patel
2023-09-12 17:49 ` [PATCH v8 13/16] irqchip: Add RISC-V advanced PLIC driver for direct-mode Anup Patel
2023-09-25 7:56 ` Sunil V L
2023-09-25 8:00 ` Sunil V L
2023-09-28 4:38 ` Anup Patel
2023-09-12 17:49 ` [PATCH v8 14/16] irqchip/riscv-aplic: Add support for MSI-mode Anup Patel
2023-09-12 17:49 ` [PATCH v8 15/16] RISC-V: Select APLIC and IMSIC drivers Anup Patel
2023-09-12 17:49 ` [PATCH v8 16/16] MAINTAINERS: Add entry for RISC-V AIA drivers Anup Patel
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