* [PATCH v2 4/7] cxl: Fix a checkpatch error
[not found] <CGME20230922113317epcas2p4f6b9ee86aeead4ce8b19473379ecf4bb@epcas2p4.samsung.com>
@ 2023-09-22 11:36 ` Jeongtae Park
2023-09-25 10:09 ` Jonathan Cameron
2023-09-28 1:32 ` Davidlohr Bueso
0 siblings, 2 replies; 3+ messages in thread
From: Jeongtae Park @ 2023-09-22 11:36 UTC (permalink / raw)
To: Dan Williams, Alison Schofield, Vishal Verma, Ben Widawsky,
Jonathan Cameron, Dave Jiang, Davidlohr Bueso, Fan Ni, linux-cxl
Cc: linux-kernel, Greg Kroah-Hartman, Kyungsan Kim, Wonjae Lee,
Hojin Nam, Junhyeok Im, Jehoon Park, Jeongtae Park, Jeongtae Park
ERROR: Macros with complex values should be enclosed in parentheses
Signed-off-by: Jeongtae Park <jtp.park@samsung.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
---
drivers/cxl/cxl.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 76d92561af29..545381355efb 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -142,7 +142,7 @@ static inline int ways_to_eiw(unsigned int ways, u8 *eiw)
#define CXL_RAS_HEADER_LOG_OFFSET 0x18
#define CXL_RAS_CAPABILITY_LENGTH 0x58
#define CXL_HEADERLOG_SIZE SZ_512
-#define CXL_HEADERLOG_SIZE_U32 SZ_512 / sizeof(u32)
+#define CXL_HEADERLOG_SIZE_U32 (SZ_512 / sizeof(u32))
/* CXL 2.0 8.2.8.1 Device Capabilities Array Register */
#define CXLDEV_CAP_ARRAY_OFFSET 0x0
--
2.34.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v2 4/7] cxl: Fix a checkpatch error
2023-09-22 11:36 ` [PATCH v2 4/7] cxl: Fix a checkpatch error Jeongtae Park
@ 2023-09-25 10:09 ` Jonathan Cameron
2023-09-28 1:32 ` Davidlohr Bueso
1 sibling, 0 replies; 3+ messages in thread
From: Jonathan Cameron @ 2023-09-25 10:09 UTC (permalink / raw)
To: Jeongtae Park
Cc: Dan Williams, Alison Schofield, Vishal Verma, Ben Widawsky,
Dave Jiang, Davidlohr Bueso, Fan Ni, linux-cxl, linux-kernel,
Greg Kroah-Hartman, Kyungsan Kim, Wonjae Lee, Hojin Nam,
Junhyeok Im, Jehoon Park, Jeongtae Park
On Fri, 22 Sep 2023 20:36:04 +0900
Jeongtae Park <jtp.park@samsung.com> wrote:
> ERROR: Macros with complex values should be enclosed in parentheses
>
> Signed-off-by: Jeongtae Park <jtp.park@samsung.com>
> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
I checked the places this is used and it won't result in any functional
change so good to tidy it up.
> ---
> drivers/cxl/cxl.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index 76d92561af29..545381355efb 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -142,7 +142,7 @@ static inline int ways_to_eiw(unsigned int ways, u8 *eiw)
> #define CXL_RAS_HEADER_LOG_OFFSET 0x18
> #define CXL_RAS_CAPABILITY_LENGTH 0x58
> #define CXL_HEADERLOG_SIZE SZ_512
> -#define CXL_HEADERLOG_SIZE_U32 SZ_512 / sizeof(u32)
> +#define CXL_HEADERLOG_SIZE_U32 (SZ_512 / sizeof(u32))
>
> /* CXL 2.0 8.2.8.1 Device Capabilities Array Register */
> #define CXLDEV_CAP_ARRAY_OFFSET 0x0
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v2 4/7] cxl: Fix a checkpatch error
2023-09-22 11:36 ` [PATCH v2 4/7] cxl: Fix a checkpatch error Jeongtae Park
2023-09-25 10:09 ` Jonathan Cameron
@ 2023-09-28 1:32 ` Davidlohr Bueso
1 sibling, 0 replies; 3+ messages in thread
From: Davidlohr Bueso @ 2023-09-28 1:32 UTC (permalink / raw)
To: Jeongtae Park
Cc: Dan Williams, Alison Schofield, Vishal Verma, Ben Widawsky,
Jonathan Cameron, Dave Jiang, Fan Ni, linux-cxl, linux-kernel,
Greg Kroah-Hartman, Kyungsan Kim, Wonjae Lee, Hojin Nam,
Junhyeok Im, Jehoon Park, Jeongtae Park
On Fri, 22 Sep 2023, Jeongtae Park wrote:
>ERROR: Macros with complex values should be enclosed in parentheses
>
>Signed-off-by: Jeongtae Park <jtp.park@samsung.com>
>Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
>---
> drivers/cxl/cxl.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
>index 76d92561af29..545381355efb 100644
>--- a/drivers/cxl/cxl.h
>+++ b/drivers/cxl/cxl.h
>@@ -142,7 +142,7 @@ static inline int ways_to_eiw(unsigned int ways, u8 *eiw)
> #define CXL_RAS_HEADER_LOG_OFFSET 0x18
> #define CXL_RAS_CAPABILITY_LENGTH 0x58
> #define CXL_HEADERLOG_SIZE SZ_512
>-#define CXL_HEADERLOG_SIZE_U32 SZ_512 / sizeof(u32)
>+#define CXL_HEADERLOG_SIZE_U32 (SZ_512 / sizeof(u32))
>
> /* CXL 2.0 8.2.8.1 Device Capabilities Array Register */
> #define CXLDEV_CAP_ARRAY_OFFSET 0x0
>--
>2.34.1
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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[not found] <CGME20230922113317epcas2p4f6b9ee86aeead4ce8b19473379ecf4bb@epcas2p4.samsung.com>
2023-09-22 11:36 ` [PATCH v2 4/7] cxl: Fix a checkpatch error Jeongtae Park
2023-09-25 10:09 ` Jonathan Cameron
2023-09-28 1:32 ` Davidlohr Bueso
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