From: Sunil V L <sunilvl@ventanamicro.com>
To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-acpi@vger.kernel.org
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
"Rafael J . Wysocki" <rafael@kernel.org>,
Len Brown <lenb@kernel.org>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Andrew Jones <ajones@ventanamicro.com>,
Conor Dooley <conor.dooley@microchip.com>,
Anup Patel <apatel@ventanamicro.com>,
Ard Biesheuvel <ardb@kernel.org>,
Alexandre Ghiti <alexghiti@rivosinc.com>,
Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
Atish Kumar Patra <atishp@rivosinc.com>,
Sunil V L <sunilvl@ventanamicro.com>
Subject: [PATCH v2 -next 3/4] RISC-V: cacheflush: Initialize CBO variables on ACPI systems
Date: Wed, 27 Sep 2023 22:30:14 +0530 [thread overview]
Message-ID: <20230927170015.295232-4-sunilvl@ventanamicro.com> (raw)
In-Reply-To: <20230927170015.295232-1-sunilvl@ventanamicro.com>
Using new interface to get the CBO block size information in RHCT,
initialize the variables on ACPI platforms.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
arch/riscv/mm/cacheflush.c | 37 +++++++++++++++++++++++++++++++------
1 file changed, 31 insertions(+), 6 deletions(-)
diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c
index f1387272a551..8e59644e473c 100644
--- a/arch/riscv/mm/cacheflush.c
+++ b/arch/riscv/mm/cacheflush.c
@@ -3,7 +3,9 @@
* Copyright (C) 2017 SiFive
*/
+#include <linux/acpi.h>
#include <linux/of.h>
+#include <asm/acpi.h>
#include <asm/cacheflush.h>
#ifdef CONFIG_SMP
@@ -124,15 +126,38 @@ void __init riscv_init_cbo_blocksizes(void)
unsigned long cbom_hartid, cboz_hartid;
u32 cbom_block_size = 0, cboz_block_size = 0;
struct device_node *node;
+ struct acpi_table_header *rhct;
+ acpi_status status;
+ unsigned int cpu;
+
+ if (!acpi_disabled) {
+ status = acpi_get_table(ACPI_SIG_RHCT, 0, &rhct);
+ if (ACPI_FAILURE(status))
+ return;
+ }
- for_each_of_cpu_node(node) {
- /* set block-size for cbom and/or cboz extension if available */
- cbo_get_block_size(node, "riscv,cbom-block-size",
- &cbom_block_size, &cbom_hartid);
- cbo_get_block_size(node, "riscv,cboz-block-size",
- &cboz_block_size, &cboz_hartid);
+ for_each_possible_cpu(cpu) {
+ if (acpi_disabled) {
+ node = of_cpu_device_node_get(cpu);
+ if (!node) {
+ pr_warn("Unable to find cpu node\n");
+ continue;
+ }
+
+ /* set block-size for cbom and/or cboz extension if available */
+ cbo_get_block_size(node, "riscv,cbom-block-size",
+ &cbom_block_size, &cbom_hartid);
+ cbo_get_block_size(node, "riscv,cboz-block-size",
+ &cboz_block_size, &cboz_hartid);
+ } else {
+ acpi_get_cbo_block_size(rhct, cpu, &cbom_block_size,
+ &cboz_block_size, NULL);
+ }
}
+ if (!acpi_disabled && rhct)
+ acpi_put_table((struct acpi_table_header *)rhct);
+
if (cbom_block_size)
riscv_cbom_block_size = cbom_block_size;
--
2.39.2
next prev parent reply other threads:[~2023-09-27 17:00 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-27 17:00 [PATCH v2 -next 0/4] RISC-V: ACPI improvements Sunil V L
2023-09-27 17:00 ` [PATCH v2 -next 1/4] RISC-V: ACPI: Enhance acpi_os_ioremap with MMIO remapping Sunil V L
2023-10-02 15:53 ` Conor Dooley
2023-10-03 18:53 ` Alexandre Ghiti
2023-10-04 10:33 ` Sunil V L
2023-09-27 17:00 ` [PATCH v2 -next 2/4] RISC-V: ACPI: RHCT: Add function to get CBO block sizes Sunil V L
2023-09-27 17:00 ` Sunil V L [this message]
2023-10-02 15:50 ` [PATCH v2 -next 3/4] RISC-V: cacheflush: Initialize CBO variables on ACPI systems Conor Dooley
2023-10-03 19:50 ` Samuel Holland
2023-10-04 4:22 ` Sunil V L
2023-10-04 8:33 ` Andrew Jones
2023-10-04 10:13 ` Sunil V L
2023-09-27 17:00 ` [PATCH v2 -next 4/4] clocksource/timer-riscv: ACPI: Add timer_cannot_wakeup_cpu Sunil V L
2023-09-27 20:15 ` Samuel Holland
2023-10-02 15:46 ` Conor Dooley
2023-10-04 8:38 ` Andrew Jones
2023-10-11 9:14 ` Daniel Lezcano
2023-10-27 18:23 ` [tip: timers/core] " tip-bot2 for Sunil V L
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