public inbox for linux-kernel@vger.kernel.org
 help / color / mirror / Atom feed
From: Anup Patel <apatel@ventanamicro.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Frank Rowand <frowand.list@gmail.com>,
	Conor Dooley <conor+dt@kernel.org>
Cc: Atish Patra <atishp@atishpatra.org>,
	Andrew Jones <ajones@ventanamicro.com>,
	Sunil V L <sunilvl@ventanamicro.com>,
	Saravana Kannan <saravanak@google.com>,
	Anup Patel <anup@brainfault.org>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, Anup Patel <apatel@ventanamicro.com>
Subject: [PATCH v9 03/15] drivers: irqchip/riscv-intc: Mark all INTC nodes as initialized
Date: Thu, 28 Sep 2023 11:41:55 +0530	[thread overview]
Message-ID: <20230928061207.1841513-4-apatel@ventanamicro.com> (raw)
In-Reply-To: <20230928061207.1841513-1-apatel@ventanamicro.com>

The RISC-V INTC local interrupts are per-HART (or per-CPU) so we
create INTC IRQ domain only for the INTC node belonging to the boot
HART. This means only the boot HART INTC node will be marked as
initialized and other INTC nodes won't be marked which results
downstream interrupt controllers (such as PLIC, IMSIC and APLIC
direct-mode) not being probed due to missing device suppliers.

To address this issue, we mark all INTC node for which we don't
create IRQ domain as initialized.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 drivers/irqchip/irq-riscv-intc.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
index 4adeee1bc391..e8d01b14ccdd 100644
--- a/drivers/irqchip/irq-riscv-intc.c
+++ b/drivers/irqchip/irq-riscv-intc.c
@@ -155,8 +155,16 @@ static int __init riscv_intc_init(struct device_node *node,
 	 * for each INTC DT node. We only need to do INTC initialization
 	 * for the INTC DT node belonging to boot CPU (or boot HART).
 	 */
-	if (riscv_hartid_to_cpuid(hartid) != smp_processor_id())
+	if (riscv_hartid_to_cpuid(hartid) != smp_processor_id()) {
+		/*
+		 * The INTC nodes of each CPU are suppliers for downstream
+		 * interrupt controllers (such as PLIC, IMSIC and APLIC
+		 * direct-mode) so we should mark an INTC node as initialized
+		 * if we are not creating IRQ domain for it.
+		 */
+		fwnode_dev_initialized(of_fwnode_handle(node), true);
 		return 0;
+	}
 
 	return riscv_intc_init_common(of_node_to_fwnode(node));
 }
-- 
2.34.1


  parent reply	other threads:[~2023-09-28  6:13 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-28  6:11 [PATCH v9 00/15] Linux RISC-V AIA Support Anup Patel
2023-09-28  6:11 ` [PATCH v9 01/15] RISC-V: Don't fail in riscv_of_parent_hartid() for disabled HARTs Anup Patel
2023-09-28  6:11 ` [PATCH v9 02/15] of: property: Add fw_devlink support for msi-parent Anup Patel
2023-09-28 14:39   ` Rob Herring
2023-09-29  0:09     ` Saravana Kannan
2023-09-28  6:11 ` Anup Patel [this message]
2023-09-28  6:11 ` [PATCH v9 04/15] irqchip/sifive-plic: Fix syscore registration for multi-socket systems Anup Patel
2023-09-28  6:11 ` [PATCH v9 05/15] irqchip/sifive-plic: Convert PLIC driver into a platform driver Anup Patel
2023-09-29 12:32   ` Marc Zyngier
2023-10-02 15:18     ` Anup Patel
2023-09-28  6:11 ` [PATCH v9 06/15] irqchip/riscv-intc: Add support for RISC-V AIA Anup Patel
2023-09-28  6:11 ` [PATCH v9 07/15] dt-bindings: interrupt-controller: Add RISC-V incoming MSI controller Anup Patel
2023-09-28  6:12 ` [PATCH v9 08/15] irqchip: Add RISC-V incoming MSI controller early driver Anup Patel
2023-09-28  6:12 ` [PATCH v9 09/15] irqchip/riscv-imsic: Add support for platform MSI irqdomain Anup Patel
2023-09-28  6:12 ` [PATCH v9 10/15] irqchip/riscv-imsic: Add support for PCI " Anup Patel
2023-09-28  6:12 ` [PATCH v9 11/15] dt-bindings: interrupt-controller: Add RISC-V advanced PLIC Anup Patel
2023-09-28  6:12 ` [PATCH v9 12/15] irqchip: Add RISC-V advanced PLIC driver for direct-mode Anup Patel
2023-09-28  6:12 ` [PATCH v9 13/15] irqchip/riscv-aplic: Add support for MSI-mode Anup Patel
2023-09-28  6:12 ` [PATCH v9 14/15] RISC-V: Select APLIC and IMSIC drivers Anup Patel
2023-09-28  6:12 ` [PATCH v9 15/15] MAINTAINERS: Add entry for RISC-V AIA drivers Anup Patel

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20230928061207.1841513-4-apatel@ventanamicro.com \
    --to=apatel@ventanamicro.com \
    --cc=ajones@ventanamicro.com \
    --cc=anup@brainfault.org \
    --cc=atishp@atishpatra.org \
    --cc=conor+dt@kernel.org \
    --cc=devicetree@vger.kernel.org \
    --cc=frowand.list@gmail.com \
    --cc=krzysztof.kozlowski+dt@linaro.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-riscv@lists.infradead.org \
    --cc=maz@kernel.org \
    --cc=palmer@dabbelt.com \
    --cc=paul.walmsley@sifive.com \
    --cc=robh+dt@kernel.org \
    --cc=saravanak@google.com \
    --cc=sunilvl@ventanamicro.com \
    --cc=tglx@linutronix.de \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox