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[198.0.35.241]) by smtp.gmail.com with ESMTPSA id ey1-20020a056a0038c100b0068a13b0b300sm17483758pfb.11.2023.09.30.14.01.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Sep 2023 14:01:13 -0700 (PDT) Date: Sat, 30 Sep 2023 14:01:11 -0700 From: Kees Cook To: Conor Dooley Cc: Sami Tolvanen , Paul Walmsley , Palmer Dabbelt , Albert Ou , Andrew Morton , linux-mm@kvack.org, linux-riscv@lists.infradead.org, llvm@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/2] riscv: mm: Update mmap_rnd_bits_max Message-ID: <202309301400.4E1AD87@keescook> References: <20230929211155.3910949-4-samitolvanen@google.com> <20230929211155.3910949-6-samitolvanen@google.com> <202309291452.66ED9B4D83@keescook> <20230930-emporium-share-2bbdf7074e54@spud> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20230930-emporium-share-2bbdf7074e54@spud> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, Sep 30, 2023 at 10:02:35AM +0100, Conor Dooley wrote: > On Fri, Sep 29, 2023 at 03:52:22PM -0700, Sami Tolvanen wrote: > > On Fri, Sep 29, 2023 at 2:54 PM Kees Cook wrote: > > > > > > On Fri, Sep 29, 2023 at 09:11:58PM +0000, Sami Tolvanen wrote: > > > > ARCH_MMAP_RND_BITS_MAX is based on Sv39, which leaves a few > > > > potential bits of mmap randomness on the table if we end up enabling > > > > 4/5-level paging. Update mmap_rnd_bits_max to take the final address > > > > space size into account. This increases mmap_rnd_bits_max from 24 to > > > > 33 with Sv48/57. > > > > > > > > Signed-off-by: Sami Tolvanen > > > > > > I like this. Is RISCV the only arch where the paging level can be chosen > > > at boot time? > > > > I haven't seen this elsewhere, but I also haven't looked at all the > > other architectures that closely. arm64 does something interesting > > with ARM64_VA_BITS_52, but I think we can still handle that in > > Kconfig. > > AFAIU, x86-64 can do this also: > > no4lvl [RISCV] Disable 4-level and 5-level paging modes. Forces > kernel to use 3-level paging instead. > > no5lvl [X86-64,RISCV] Disable 5-level paging mode. Forces > kernel to use 4-level paging instead. Ah-ha! Okay, well, then let's track this idea: https://github.com/KSPP/linux/issues/346 -- Kees Cook