From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Robert Richter <rrichter@amd.com>
Cc: Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Ben Widawsky <bwidawsk@kernel.org>,
Dan Williams <dan.j.williams@intel.com>,
"Davidlohr Bueso" <dave@stgolabs.net>,
Dave Jiang <dave.jiang@intel.com>,
Terry Bowman <terry.bowman@amd.com>, <linux-cxl@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>
Subject: Re: [PATCH v11 02/20] cxl/core/regs: Rename @dev to @host in struct cxl_register_map
Date: Mon, 2 Oct 2023 15:19:30 +0100 [thread overview]
Message-ID: <20231002151930.0000297f@Huawei.com> (raw)
In-Reply-To: <20230927154339.1600738-3-rrichter@amd.com>
On Wed, 27 Sep 2023 17:43:21 +0200
Robert Richter <rrichter@amd.com> wrote:
> The primary role of @dev is to host the mappings for devm operations.
> @dev is too ambiguous as a name. I.e. when does @dev refer to the
> 'struct device *' instance that the registers belong, and when does
> @dev refer to the 'struct device *' instance hosting the mapping for
> devm operations?
>
> Clarify the role of @dev in cxl_register_map by renaming it to @host.
> Also, rename local variables to 'host' where map->host is used.
>
> Add Fixes: tag as the fix in the next patch depends on this change.
>
> Fixes: 5d2ffbe4b81a ("cxl/port: Store the downstream port's Component Register mappings in struct cxl_dport")
> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> Signed-off-by: Robert Richter <rrichter@amd.com>
Good cleanup.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
> drivers/cxl/core/hdm.c | 2 +-
> drivers/cxl/core/port.c | 4 ++--
> drivers/cxl/core/regs.c | 28 ++++++++++++++--------------
> drivers/cxl/cxl.h | 4 ++--
> drivers/cxl/pci.c | 2 +-
> 5 files changed, 20 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
> index 4449b34a80cc..11d9971f3e8c 100644
> --- a/drivers/cxl/core/hdm.c
> +++ b/drivers/cxl/core/hdm.c
> @@ -85,7 +85,7 @@ static int map_hdm_decoder_regs(struct cxl_port *port, void __iomem *crb,
> struct cxl_component_regs *regs)
> {
> struct cxl_register_map map = {
> - .dev = &port->dev,
> + .host = &port->dev,
> .resource = port->component_reg_phys,
> .base = crb,
> .max_size = CXL_COMPONENT_REG_BLOCK_SIZE,
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index d4572a02989a..033651a5da30 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -691,14 +691,14 @@ static struct cxl_port *cxl_port_alloc(struct device *uport_dev,
> return ERR_PTR(rc);
> }
>
> -static int cxl_setup_comp_regs(struct device *dev, struct cxl_register_map *map,
> +static int cxl_setup_comp_regs(struct device *host, struct cxl_register_map *map,
> resource_size_t component_reg_phys)
> {
> if (component_reg_phys == CXL_RESOURCE_NONE)
> return 0;
>
> *map = (struct cxl_register_map) {
> - .dev = dev,
> + .host = host,
> .reg_type = CXL_REGLOC_RBI_COMPONENT,
> .resource = component_reg_phys,
> .max_size = CXL_COMPONENT_REG_BLOCK_SIZE,
> diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
> index 6281127b3e9d..e0fbe964f6f0 100644
> --- a/drivers/cxl/core/regs.c
> +++ b/drivers/cxl/core/regs.c
> @@ -204,7 +204,7 @@ int cxl_map_component_regs(const struct cxl_register_map *map,
> struct cxl_component_regs *regs,
> unsigned long map_mask)
> {
> - struct device *dev = map->dev;
> + struct device *host = map->host;
> struct mapinfo {
> const struct cxl_reg_map *rmap;
> void __iomem **addr;
> @@ -225,7 +225,7 @@ int cxl_map_component_regs(const struct cxl_register_map *map,
> continue;
> phys_addr = map->resource + mi->rmap->offset;
> length = mi->rmap->size;
> - *(mi->addr) = devm_cxl_iomap_block(dev, phys_addr, length);
> + *(mi->addr) = devm_cxl_iomap_block(host, phys_addr, length);
> if (!*(mi->addr))
> return -ENOMEM;
> }
> @@ -237,7 +237,7 @@ EXPORT_SYMBOL_NS_GPL(cxl_map_component_regs, CXL);
> int cxl_map_device_regs(const struct cxl_register_map *map,
> struct cxl_device_regs *regs)
> {
> - struct device *dev = map->dev;
> + struct device *host = map->host;
> resource_size_t phys_addr = map->resource;
> struct mapinfo {
> const struct cxl_reg_map *rmap;
> @@ -259,7 +259,7 @@ int cxl_map_device_regs(const struct cxl_register_map *map,
>
> addr = phys_addr + mi->rmap->offset;
> length = mi->rmap->size;
> - *(mi->addr) = devm_cxl_iomap_block(dev, addr, length);
> + *(mi->addr) = devm_cxl_iomap_block(host, addr, length);
> if (!*(mi->addr))
> return -ENOMEM;
> }
> @@ -309,7 +309,7 @@ int cxl_find_regblock_instance(struct pci_dev *pdev, enum cxl_regloc_type type,
> int regloc, i;
>
> *map = (struct cxl_register_map) {
> - .dev = &pdev->dev,
> + .host = &pdev->dev,
> .resource = CXL_RESOURCE_NONE,
> };
>
> @@ -403,15 +403,15 @@ EXPORT_SYMBOL_NS_GPL(cxl_map_pmu_regs, CXL);
>
> static int cxl_map_regblock(struct cxl_register_map *map)
> {
> - struct device *dev = map->dev;
> + struct device *host = map->host;
>
> map->base = ioremap(map->resource, map->max_size);
> if (!map->base) {
> - dev_err(dev, "failed to map registers\n");
> + dev_err(host, "failed to map registers\n");
> return -ENOMEM;
> }
>
> - dev_dbg(dev, "Mapped CXL Memory Device resource %pa\n", &map->resource);
> + dev_dbg(host, "Mapped CXL Memory Device resource %pa\n", &map->resource);
> return 0;
> }
>
> @@ -425,28 +425,28 @@ static int cxl_probe_regs(struct cxl_register_map *map)
> {
> struct cxl_component_reg_map *comp_map;
> struct cxl_device_reg_map *dev_map;
> - struct device *dev = map->dev;
> + struct device *host = map->host;
> void __iomem *base = map->base;
>
> switch (map->reg_type) {
> case CXL_REGLOC_RBI_COMPONENT:
> comp_map = &map->component_map;
> - cxl_probe_component_regs(dev, base, comp_map);
> - dev_dbg(dev, "Set up component registers\n");
> + cxl_probe_component_regs(host, base, comp_map);
> + dev_dbg(host, "Set up component registers\n");
> break;
> case CXL_REGLOC_RBI_MEMDEV:
> dev_map = &map->device_map;
> - cxl_probe_device_regs(dev, base, dev_map);
> + cxl_probe_device_regs(host, base, dev_map);
> if (!dev_map->status.valid || !dev_map->mbox.valid ||
> !dev_map->memdev.valid) {
> - dev_err(dev, "registers not found: %s%s%s\n",
> + dev_err(host, "registers not found: %s%s%s\n",
> !dev_map->status.valid ? "status " : "",
> !dev_map->mbox.valid ? "mbox " : "",
> !dev_map->memdev.valid ? "memdev " : "");
> return -ENXIO;
> }
>
> - dev_dbg(dev, "Probing device registers...\n");
> + dev_dbg(host, "Probing device registers...\n");
> break;
> default:
> break;
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index 76d92561af29..b5b015b661ea 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -247,7 +247,7 @@ struct cxl_pmu_reg_map {
>
> /**
> * struct cxl_register_map - DVSEC harvested register block mapping parameters
> - * @dev: device for devm operations and logging
> + * @host: device for devm operations and logging
> * @base: virtual base of the register-block-BAR + @block_offset
> * @resource: physical resource base of the register block
> * @max_size: maximum mapping size to perform register search
> @@ -257,7 +257,7 @@ struct cxl_pmu_reg_map {
> * @pmu_map: cxl_reg_maps for CXL Performance Monitoring Units
> */
> struct cxl_register_map {
> - struct device *dev;
> + struct device *host;
> void __iomem *base;
> resource_size_t resource;
> resource_size_t max_size;
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index 44a21ab7add5..f9d852957809 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
> @@ -484,7 +484,7 @@ static int cxl_rcrb_get_comp_regs(struct pci_dev *pdev,
> resource_size_t component_reg_phys;
>
> *map = (struct cxl_register_map) {
> - .dev = &pdev->dev,
> + .host = &pdev->dev,
> .resource = CXL_RESOURCE_NONE,
> };
>
next prev parent reply other threads:[~2023-10-02 14:19 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-27 15:43 [PATCH v11 00/20] cxl/pci: Add support for RCH RAS error handling Robert Richter
2023-09-27 15:43 ` [PATCH v11 01/20] cxl/port: Fix release of RCD endpoints Robert Richter
2023-10-02 14:14 ` Jonathan Cameron
2023-09-27 15:43 ` [PATCH v11 02/20] cxl/core/regs: Rename @dev to @host in struct cxl_register_map Robert Richter
2023-10-02 14:19 ` Jonathan Cameron [this message]
2023-09-27 15:43 ` [PATCH v11 03/20] cxl/port: Fix @host confusion in cxl_dport_setup_regs() Robert Richter
2023-10-02 14:32 ` Jonathan Cameron
2023-09-27 15:43 ` [PATCH v11 04/20] cxl/port: Rename @comp_map to @reg_map in struct cxl_register_map Robert Richter
2023-10-02 14:34 ` Jonathan Cameron
2023-10-09 14:27 ` Terry Bowman
2023-09-27 15:43 ` [PATCH v11 05/20] cxl/port: Pre-initialize component register mappings Robert Richter
2023-09-27 15:43 ` [PATCH v11 06/20] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state Robert Richter
2023-09-27 15:43 ` [PATCH v11 07/20] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability Robert Richter
2023-10-02 14:43 ` Jonathan Cameron
2023-10-09 14:35 ` Terry Bowman
2023-10-16 14:09 ` Robert Richter
2023-09-27 15:43 ` [PATCH v11 08/20] cxl/pci: Remove Component Register base address from struct cxl_dev_state Robert Richter
2023-09-27 15:43 ` [PATCH v11 09/20] cxl/port: Remove Component Register base address from struct cxl_port Robert Richter
2023-09-27 15:43 ` [PATCH v11 10/20] cxl/pci: Introduce config option PCIEAER_CXL Robert Richter
2023-10-02 14:46 ` Jonathan Cameron
2023-10-09 14:44 ` Terry Bowman
2023-10-16 13:40 ` Terry Bowman
2023-10-16 14:08 ` Jonathan Cameron
2023-09-27 15:43 ` [PATCH v11 11/20] cxl/pci: Add RCH downstream port AER register discovery Robert Richter
2023-10-02 14:53 ` Jonathan Cameron
2023-10-09 14:55 ` Terry Bowman
2023-09-27 15:43 ` [PATCH v11 12/20] PCI/AER: Refactor cper_print_aer() for use by CXL driver module Robert Richter
2023-09-27 15:43 ` [PATCH v11 13/20] cxl/pci: Update CXL error logging to use RAS register address Robert Richter
2023-09-27 15:43 ` [PATCH v11 14/20] cxl/pci: Map RCH downstream AER registers for logging protocol errors Robert Richter
2023-10-02 14:56 ` Jonathan Cameron
2023-10-09 14:56 ` Terry Bowman
2023-09-27 15:43 ` [PATCH v11 15/20] cxl/pci: Add RCH downstream port error logging Robert Richter
2023-09-27 15:43 ` [PATCH v11 16/20] cxl/pci: Disable root port interrupts in RCH mode Robert Richter
2023-09-27 15:43 ` [PATCH v11 17/20] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler Robert Richter
2023-09-27 15:43 ` [PATCH v11 18/20] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling Robert Richter
2023-09-27 15:43 ` [PATCH v11 19/20] cxl/core/regs: Rename phys_addr in cxl_map_component_regs() Robert Richter
2023-09-27 15:43 ` [PATCH v11 20/20] cxl/core/regs: Rework cxl_map_pmu_regs() to use map->dev for devm Robert Richter
2023-10-02 15:01 ` Jonathan Cameron
2023-09-27 16:04 ` [PATCH v11 00/20] cxl/pci: Add support for RCH RAS error handling Robert Richter
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20231002151930.0000297f@Huawei.com \
--to=jonathan.cameron@huawei.com \
--cc=alison.schofield@intel.com \
--cc=bhelgaas@google.com \
--cc=bwidawsk@kernel.org \
--cc=dan.j.williams@intel.com \
--cc=dave.jiang@intel.com \
--cc=dave@stgolabs.net \
--cc=ira.weiny@intel.com \
--cc=linux-cxl@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=rrichter@amd.com \
--cc=terry.bowman@amd.com \
--cc=vishal.l.verma@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox