Re: [PATCH v11 14/20] cxl/pci: Map RCH downstream AER registers for logging protocol errors

Terry Bowman
2023-10-09T14:56:50Z

On 10/2/23 09:56, Jonathan Cameron wrote:
> On Wed, 27 Sep 2023 17:43:33 +0200
> Robert Richter <rrichter@amd.com> wrote:
>
>> From: Terry Bowman <terry.bowman@amd.com>
>>
>> The restricted CXL host (RCH) error handler will log protocol errors
>> using AER and RAS status registers. The AER and RAS registers need to
>> be virtually memory mapped before enabling interrupts. Create the
>> initializer function devm_cxl_setup_parent_dport() for this when the
>> endpoint is connected with the dport. The initialization sets up the
>> RCH RAS and AER mappings.
>>
>> Add 'struct cxl_regs' to 'struct cxl_dport' for saving a pointer to
>> the RCH downstream port's AER and RAS registers.
>>
>> Co-developed-by: Robert Richter <rrichter@amd.com>
>> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> As before. Co-dev just before SoB.
>
> https://elixir.bootlin.com/linux/latest/source/Documentation/process/submitting-patches.rst#L521
> This example looks like what you have here.
>
>> Signed-off-by: Robert Richter <rrichter@amd.com>
> Otherwise, LGTM
>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

Yes, we will fix.

Regards,
Terry