From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Robert Richter <rrichter@amd.com>
Cc: Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Ben Widawsky <bwidawsk@kernel.org>,
Dan Williams <dan.j.williams@intel.com>,
"Davidlohr Bueso" <dave@stgolabs.net>,
Dave Jiang <dave.jiang@intel.com>, <linux-cxl@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>,
Terry Bowman <terry.bowman@amd.com>
Subject: Re: [PATCH v11 04/20] cxl/port: Rename @comp_map to @reg_map in struct cxl_register_map
Date: Mon, 2 Oct 2023 15:34:34 +0100 [thread overview]
Message-ID: <20231002153434.000073b9@Huawei.com> (raw)
In-Reply-To: <20230927154339.1600738-5-rrichter@amd.com>
On Wed, 27 Sep 2023 17:43:23 +0200
Robert Richter <rrichter@amd.com> wrote:
> Name the field @reg_map, because @reg_map->host will be used for
> mapping operations beyond component registers (i.e. AER registers).
> This is valid for all occurrences of @comp_map. Change them all.
>
> Signed-off-by: Robert Richter <rrichter@amd.com>
Makes sense. Can we pull the one I moaned about in the previous
patch into this one?
That way the renames are all together.
If not, I'm fine with just moaning :) Whichever patch split
you go with across this and previous...
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.co>
> ---
> drivers/cxl/core/port.c | 2 +-
> drivers/cxl/cxl.h | 4 ++--
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index 99df86d72dbc..b993dea61436 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -712,7 +712,7 @@ static int cxl_port_setup_regs(struct cxl_port *port,
> {
> if (dev_is_platform(port->uport_dev))
> return 0;
> - return cxl_setup_comp_regs(&port->dev, &port->comp_map,
> + return cxl_setup_comp_regs(&port->dev, &port->reg_map,
> component_reg_phys);
> }
>
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index 68abf9944383..3a51b58a66d0 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -572,7 +572,7 @@ struct cxl_dax_region {
> * @regions: cxl_region_ref instances, regions mapped by this port
> * @parent_dport: dport that points to this port in the parent
> * @decoder_ida: allocator for decoder ids
> - * @comp_map: component register capability mappings
> + * @reg_map: component and ras register mapping parameters
> * @nr_dports: number of entries in @dports
> * @hdm_end: track last allocated HDM decoder instance for allocation ordering
> * @commit_end: cursor to track highest committed decoder for commit ordering
> @@ -592,7 +592,7 @@ struct cxl_port {
> struct xarray regions;
> struct cxl_dport *parent_dport;
> struct ida decoder_ida;
> - struct cxl_register_map comp_map;
> + struct cxl_register_map reg_map;
> int nr_dports;
> int hdm_end;
> int commit_end;
next prev parent reply other threads:[~2023-10-02 14:34 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-27 15:43 [PATCH v11 00/20] cxl/pci: Add support for RCH RAS error handling Robert Richter
2023-09-27 15:43 ` [PATCH v11 01/20] cxl/port: Fix release of RCD endpoints Robert Richter
2023-10-02 14:14 ` Jonathan Cameron
2023-09-27 15:43 ` [PATCH v11 02/20] cxl/core/regs: Rename @dev to @host in struct cxl_register_map Robert Richter
2023-10-02 14:19 ` Jonathan Cameron
2023-09-27 15:43 ` [PATCH v11 03/20] cxl/port: Fix @host confusion in cxl_dport_setup_regs() Robert Richter
2023-10-02 14:32 ` Jonathan Cameron
2023-09-27 15:43 ` [PATCH v11 04/20] cxl/port: Rename @comp_map to @reg_map in struct cxl_register_map Robert Richter
2023-10-02 14:34 ` Jonathan Cameron [this message]
2023-10-09 14:27 ` Terry Bowman
2023-09-27 15:43 ` [PATCH v11 05/20] cxl/port: Pre-initialize component register mappings Robert Richter
2023-09-27 15:43 ` [PATCH v11 06/20] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state Robert Richter
2023-09-27 15:43 ` [PATCH v11 07/20] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability Robert Richter
2023-10-02 14:43 ` Jonathan Cameron
2023-10-09 14:35 ` Terry Bowman
2023-10-16 14:09 ` Robert Richter
2023-09-27 15:43 ` [PATCH v11 08/20] cxl/pci: Remove Component Register base address from struct cxl_dev_state Robert Richter
2023-09-27 15:43 ` [PATCH v11 09/20] cxl/port: Remove Component Register base address from struct cxl_port Robert Richter
2023-09-27 15:43 ` [PATCH v11 10/20] cxl/pci: Introduce config option PCIEAER_CXL Robert Richter
2023-10-02 14:46 ` Jonathan Cameron
2023-10-09 14:44 ` Terry Bowman
2023-10-16 13:40 ` Terry Bowman
2023-10-16 14:08 ` Jonathan Cameron
2023-09-27 15:43 ` [PATCH v11 11/20] cxl/pci: Add RCH downstream port AER register discovery Robert Richter
2023-10-02 14:53 ` Jonathan Cameron
2023-10-09 14:55 ` Terry Bowman
2023-09-27 15:43 ` [PATCH v11 12/20] PCI/AER: Refactor cper_print_aer() for use by CXL driver module Robert Richter
2023-09-27 15:43 ` [PATCH v11 13/20] cxl/pci: Update CXL error logging to use RAS register address Robert Richter
2023-09-27 15:43 ` [PATCH v11 14/20] cxl/pci: Map RCH downstream AER registers for logging protocol errors Robert Richter
2023-10-02 14:56 ` Jonathan Cameron
2023-10-09 14:56 ` Terry Bowman
2023-09-27 15:43 ` [PATCH v11 15/20] cxl/pci: Add RCH downstream port error logging Robert Richter
2023-09-27 15:43 ` [PATCH v11 16/20] cxl/pci: Disable root port interrupts in RCH mode Robert Richter
2023-09-27 15:43 ` [PATCH v11 17/20] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler Robert Richter
2023-09-27 15:43 ` [PATCH v11 18/20] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling Robert Richter
2023-09-27 15:43 ` [PATCH v11 19/20] cxl/core/regs: Rename phys_addr in cxl_map_component_regs() Robert Richter
2023-09-27 15:43 ` [PATCH v11 20/20] cxl/core/regs: Rework cxl_map_pmu_regs() to use map->dev for devm Robert Richter
2023-10-02 15:01 ` Jonathan Cameron
2023-09-27 16:04 ` [PATCH v11 00/20] cxl/pci: Add support for RCH RAS error handling Robert Richter
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