From: "David E. Box" <david.e.box@linux.intel.com>
To: linux-kernel@vger.kernel.org,
platform-driver-x86@vger.kernel.org,
ilpo.jarvinen@linux.intel.com, rajvi.jingar@linux.intel.com
Subject: [PATCH V2 01/13] platform/x86/intel/vsec: Move structures to header
Date: Tue, 3 Oct 2023 19:02:10 -0700 [thread overview]
Message-ID: <20231004020222.193445-2-david.e.box@linux.intel.com> (raw)
In-Reply-To: <20231004020222.193445-1-david.e.box@linux.intel.com>
In preparation for exporting an API to register Intel Vendor Specific
Extended Capabilities (VSEC) from other drivers, move needed structures to
the header file.
Signed-off-by: David E. Box <david.e.box@linux.intel.com>
---
V2 - New patch splitting previous PATCH 1
drivers/platform/x86/intel/vsec.c | 35 ------------------------------
drivers/platform/x86/intel/vsec.h | 36 +++++++++++++++++++++++++++++++
2 files changed, 36 insertions(+), 35 deletions(-)
diff --git a/drivers/platform/x86/intel/vsec.c b/drivers/platform/x86/intel/vsec.c
index c1f9e4471b28..e82a009be630 100644
--- a/drivers/platform/x86/intel/vsec.c
+++ b/drivers/platform/x86/intel/vsec.c
@@ -24,13 +24,6 @@
#include "vsec.h"
-/* Intel DVSEC offsets */
-#define INTEL_DVSEC_ENTRIES 0xA
-#define INTEL_DVSEC_SIZE 0xB
-#define INTEL_DVSEC_TABLE 0xC
-#define INTEL_DVSEC_TABLE_BAR(x) ((x) & GENMASK(2, 0))
-#define INTEL_DVSEC_TABLE_OFFSET(x) ((x) & GENMASK(31, 3))
-#define TABLE_OFFSET_SHIFT 3
#define PMT_XA_START 0
#define PMT_XA_MAX INT_MAX
#define PMT_XA_LIMIT XA_LIMIT(PMT_XA_START, PMT_XA_MAX)
@@ -39,34 +32,6 @@ static DEFINE_IDA(intel_vsec_ida);
static DEFINE_IDA(intel_vsec_sdsi_ida);
static DEFINE_XARRAY_ALLOC(auxdev_array);
-/**
- * struct intel_vsec_header - Common fields of Intel VSEC and DVSEC registers.
- * @rev: Revision ID of the VSEC/DVSEC register space
- * @length: Length of the VSEC/DVSEC register space
- * @id: ID of the feature
- * @num_entries: Number of instances of the feature
- * @entry_size: Size of the discovery table for each feature
- * @tbir: BAR containing the discovery tables
- * @offset: BAR offset of start of the first discovery table
- */
-struct intel_vsec_header {
- u8 rev;
- u16 length;
- u16 id;
- u8 num_entries;
- u8 entry_size;
- u8 tbir;
- u32 offset;
-};
-
-enum intel_vsec_id {
- VSEC_ID_TELEMETRY = 2,
- VSEC_ID_WATCHER = 3,
- VSEC_ID_CRASHLOG = 4,
- VSEC_ID_SDSI = 65,
- VSEC_ID_TPMI = 66,
-};
-
static const char *intel_vsec_name(enum intel_vsec_id id)
{
switch (id) {
diff --git a/drivers/platform/x86/intel/vsec.h b/drivers/platform/x86/intel/vsec.h
index 0fd042c171ba..8900cb95afd3 100644
--- a/drivers/platform/x86/intel/vsec.h
+++ b/drivers/platform/x86/intel/vsec.h
@@ -11,9 +11,45 @@
#define VSEC_CAP_SDSI BIT(3)
#define VSEC_CAP_TPMI BIT(4)
+/* Intel DVSEC offsets */
+#define INTEL_DVSEC_ENTRIES 0xA
+#define INTEL_DVSEC_SIZE 0xB
+#define INTEL_DVSEC_TABLE 0xC
+#define INTEL_DVSEC_TABLE_BAR(x) ((x) & GENMASK(2, 0))
+#define INTEL_DVSEC_TABLE_OFFSET(x) ((x) & GENMASK(31, 3))
+#define TABLE_OFFSET_SHIFT 3
+
struct pci_dev;
struct resource;
+enum intel_vsec_id {
+ VSEC_ID_TELEMETRY = 2,
+ VSEC_ID_WATCHER = 3,
+ VSEC_ID_CRASHLOG = 4,
+ VSEC_ID_SDSI = 65,
+ VSEC_ID_TPMI = 66,
+};
+
+/**
+ * struct intel_vsec_header - Common fields of Intel VSEC and DVSEC registers.
+ * @rev: Revision ID of the VSEC/DVSEC register space
+ * @length: Length of the VSEC/DVSEC register space
+ * @id: ID of the feature
+ * @num_entries: Number of instances of the feature
+ * @entry_size: Size of the discovery table for each feature
+ * @tbir: BAR containing the discovery tables
+ * @offset: BAR offset of start of the first discovery table
+ */
+struct intel_vsec_header {
+ u8 rev;
+ u16 length;
+ u16 id;
+ u8 num_entries;
+ u8 entry_size;
+ u8 tbir;
+ u32 offset;
+};
+
enum intel_vsec_quirks {
/* Watcher feature not supported */
VSEC_QUIRK_NO_WATCHER = BIT(0),
--
2.34.1
next prev parent reply other threads:[~2023-10-04 2:02 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-04 2:02 [PATCH V2 00/13] intel_pmc: Add telemetry API to read counters David E. Box
2023-10-04 2:02 ` David E. Box [this message]
2023-10-04 7:24 ` [PATCH V2 01/13] platform/x86/intel/vsec: Move structures to header Ilpo Järvinen
2023-10-04 2:02 ` [PATCH V2 02/13] platform/x86/intel/vsec: remove platform_info from vsec device structure David E. Box
2023-10-04 7:27 ` Ilpo Järvinen
2023-10-04 2:02 ` [PATCH V2 03/13] platform/x86/intel/vsec: Add intel_vsec_register David E. Box
2023-10-04 7:44 ` Ilpo Järvinen
2023-10-04 2:02 ` [PATCH V2 04/13] platform/x86/intel/vsec: Add base address field David E. Box
2023-10-04 2:02 ` [PATCH V2 05/13] platform/x86/intel/pmt: Add header to struct intel_pmt_entry David E. Box
2023-10-04 2:02 ` [PATCH V2 06/13] platform/x86/intel/pmt: telemetry: Export API to read telemetry David E. Box
2023-10-04 7:22 ` Ilpo Järvinen
2023-10-04 2:02 ` [PATCH V2 07/13] platform/x86:intel/pmc: Call pmc_get_low_power_modes from platform init David E. Box
2023-10-04 7:45 ` Ilpo Järvinen
2023-10-04 2:02 ` [PATCH V2 08/13] platform/x86/intel/pmc: Split pmc_core_ssram_get_pmc() David E. Box
2023-10-04 2:02 ` [PATCH V2 09/13] platform/x86/intel/pmc: Find and register PMC telemetry entries David E. Box
2023-10-04 2:02 ` [PATCH V2 10/13] platform/x86/intel/pmc: Display LPM requirements for multiple PMCs David E. Box
2023-10-04 2:02 ` [PATCH V2 11/13] platform/x86/intel/pmc: Retrieve LPM information using Intel PMT David E. Box
2023-10-04 2:02 ` [PATCH V2 12/13] platform/x86/intel/pmc: Read low power mode requirements for MTL-M and MTL-P David E. Box
2023-10-04 7:48 ` Ilpo Järvinen
2023-10-04 2:02 ` [PATCH V2 13/13] platform/x86/intel/pmc: Add debug attribute for Die C6 counter David E. Box
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