public inbox for linux-kernel@vger.kernel.org
 help / color / mirror / Atom feed
From: "David E. Box" <david.e.box@linux.intel.com>
To: linux-kernel@vger.kernel.org,
	platform-driver-x86@vger.kernel.org,
	ilpo.jarvinen@linux.intel.com, rajvi.jingar@linux.intel.com
Subject: [PATCH V3 01/16] platform/x86/intel/vsec: Move structures to header
Date: Wed, 11 Oct 2023 19:38:25 -0700	[thread overview]
Message-ID: <20231012023840.3845703-2-david.e.box@linux.intel.com> (raw)
In-Reply-To: <20231012023840.3845703-1-david.e.box@linux.intel.com>

In preparation for exporting an API to register Intel Vendor Specific
Extended Capabilities (VSEC) from other drivers, move needed structures to
the header file.

Signed-off-by: David E. Box <david.e.box@linux.intel.com>
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
---
V3 - No change

V2 - New patch splitting previous PATCH 1

 drivers/platform/x86/intel/vsec.c | 35 ------------------------------
 drivers/platform/x86/intel/vsec.h | 36 +++++++++++++++++++++++++++++++
 2 files changed, 36 insertions(+), 35 deletions(-)

diff --git a/drivers/platform/x86/intel/vsec.c b/drivers/platform/x86/intel/vsec.c
index ae811bb65910..6bb233a23414 100644
--- a/drivers/platform/x86/intel/vsec.c
+++ b/drivers/platform/x86/intel/vsec.c
@@ -24,13 +24,6 @@
 
 #include "vsec.h"
 
-/* Intel DVSEC offsets */
-#define INTEL_DVSEC_ENTRIES		0xA
-#define INTEL_DVSEC_SIZE		0xB
-#define INTEL_DVSEC_TABLE		0xC
-#define INTEL_DVSEC_TABLE_BAR(x)	((x) & GENMASK(2, 0))
-#define INTEL_DVSEC_TABLE_OFFSET(x)	((x) & GENMASK(31, 3))
-#define TABLE_OFFSET_SHIFT		3
 #define PMT_XA_START			0
 #define PMT_XA_MAX			INT_MAX
 #define PMT_XA_LIMIT			XA_LIMIT(PMT_XA_START, PMT_XA_MAX)
@@ -39,34 +32,6 @@ static DEFINE_IDA(intel_vsec_ida);
 static DEFINE_IDA(intel_vsec_sdsi_ida);
 static DEFINE_XARRAY_ALLOC(auxdev_array);
 
-/**
- * struct intel_vsec_header - Common fields of Intel VSEC and DVSEC registers.
- * @rev:         Revision ID of the VSEC/DVSEC register space
- * @length:      Length of the VSEC/DVSEC register space
- * @id:          ID of the feature
- * @num_entries: Number of instances of the feature
- * @entry_size:  Size of the discovery table for each feature
- * @tbir:        BAR containing the discovery tables
- * @offset:      BAR offset of start of the first discovery table
- */
-struct intel_vsec_header {
-	u8	rev;
-	u16	length;
-	u16	id;
-	u8	num_entries;
-	u8	entry_size;
-	u8	tbir;
-	u32	offset;
-};
-
-enum intel_vsec_id {
-	VSEC_ID_TELEMETRY	= 2,
-	VSEC_ID_WATCHER		= 3,
-	VSEC_ID_CRASHLOG	= 4,
-	VSEC_ID_SDSI		= 65,
-	VSEC_ID_TPMI		= 66,
-};
-
 static const char *intel_vsec_name(enum intel_vsec_id id)
 {
 	switch (id) {
diff --git a/drivers/platform/x86/intel/vsec.h b/drivers/platform/x86/intel/vsec.h
index 0a6201b4a0e9..c242c07ea69c 100644
--- a/drivers/platform/x86/intel/vsec.h
+++ b/drivers/platform/x86/intel/vsec.h
@@ -11,9 +11,45 @@
 #define VSEC_CAP_SDSI		BIT(3)
 #define VSEC_CAP_TPMI		BIT(4)
 
+/* Intel DVSEC offsets */
+#define INTEL_DVSEC_ENTRIES		0xA
+#define INTEL_DVSEC_SIZE		0xB
+#define INTEL_DVSEC_TABLE		0xC
+#define INTEL_DVSEC_TABLE_BAR(x)	((x) & GENMASK(2, 0))
+#define INTEL_DVSEC_TABLE_OFFSET(x)	((x) & GENMASK(31, 3))
+#define TABLE_OFFSET_SHIFT		3
+
 struct pci_dev;
 struct resource;
 
+enum intel_vsec_id {
+	VSEC_ID_TELEMETRY	= 2,
+	VSEC_ID_WATCHER		= 3,
+	VSEC_ID_CRASHLOG	= 4,
+	VSEC_ID_SDSI		= 65,
+	VSEC_ID_TPMI		= 66,
+};
+
+/**
+ * struct intel_vsec_header - Common fields of Intel VSEC and DVSEC registers.
+ * @rev:         Revision ID of the VSEC/DVSEC register space
+ * @length:      Length of the VSEC/DVSEC register space
+ * @id:          ID of the feature
+ * @num_entries: Number of instances of the feature
+ * @entry_size:  Size of the discovery table for each feature
+ * @tbir:        BAR containing the discovery tables
+ * @offset:      BAR offset of start of the first discovery table
+ */
+struct intel_vsec_header {
+	u8	rev;
+	u16	length;
+	u16	id;
+	u8	num_entries;
+	u8	entry_size;
+	u8	tbir;
+	u32	offset;
+};
+
 enum intel_vsec_quirks {
 	/* Watcher feature not supported */
 	VSEC_QUIRK_NO_WATCHER	= BIT(0),
-- 
2.34.1


  reply	other threads:[~2023-10-12  2:38 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-12  2:38 [PATCH V3 00/16] intel_pmc: Add telemetry API to read counters David E. Box
2023-10-12  2:38 ` David E. Box [this message]
2023-10-12  2:38 ` [PATCH V3 02/16] platform/x86/intel/vsec: remove platform_info from vsec device structure David E. Box
2023-10-12 15:31   ` Ilpo Järvinen
2023-10-12 16:55     ` David E. Box
2023-10-12  2:38 ` [PATCH V3 03/16] platform/x86/intel/vsec: Use cleanup.h David E. Box
2023-10-12  5:25   ` kernel test robot
2023-10-12 17:23     ` David E. Box
2023-10-13 10:39       ` Ilpo Järvinen
2023-10-13 18:14         ` Joe Perches
2023-10-24  5:15           ` Joe Perches
2023-10-12  5:48   ` kernel test robot
2023-10-12 14:46   ` Ilpo Järvinen
2023-10-12 17:13     ` David E. Box
2023-10-13 10:54       ` Ilpo Järvinen
2023-10-13 22:16         ` David E. Box
2023-10-16 12:02           ` Ilpo Järvinen
2023-10-12  2:38 ` [PATCH V3 04/16] platform/x86/intel/vsec: Add intel_vsec_register David E. Box
2023-10-12  2:38 ` [PATCH V3 05/16] platform/x86/intel/vsec: Add base address field David E. Box
2023-10-12  2:38 ` [PATCH V3 06/16] platform/x86/intel/pmt: Add header to struct intel_pmt_entry David E. Box
2023-10-12  2:38 ` [PATCH V3 07/16] platform/x86/intel/pmt: telemetry: Export API to read telemetry David E. Box
2023-10-12  2:38 ` [PATCH V3 08/16] platform/x86:intel/pmc: Call pmc_get_low_power_modes from platform init David E. Box
2023-10-12  2:38 ` [PATCH V3 09/16] platform/x86/intel/pmc: Allow pmc_core_ssram_init to fail David E. Box
2023-10-12 15:01   ` Ilpo Järvinen
2023-10-12 17:52     ` David E. Box
2023-10-13 11:36       ` Ilpo Järvinen
2023-10-12  2:38 ` [PATCH V3 10/16] platform/x86/intel/pmc: Split pmc_core_ssram_get_pmc() David E. Box
2023-10-12 15:14   ` Ilpo Järvinen
2023-10-12 17:28     ` David E. Box
2023-10-12  2:38 ` [PATCH V3 11/16] platform/x86/intel/pmc: Find and register PMC telemetry entries David E. Box
2023-10-12 15:17   ` Ilpo Järvinen
2023-10-12  2:38 ` [PATCH V3 12/16] platform/x86/intel/pmc: Display LPM requirements for multiple PMCs David E. Box
2023-10-12  2:38 ` [PATCH V3 13/16] platform/x86/intel/pmc: Retrieve LPM information using Intel PMT David E. Box
2023-10-12  2:38 ` [PATCH V3 14/16] platform/x86/intel/pmc: Read low power mode requirements for MTL-M and MTL-P David E. Box
2023-10-12  2:38 ` [PATCH V3 15/16] platform/x86/intel/pmc: Add debug attribute for Die C6 counter David E. Box
2023-10-12  2:38 ` [PATCH V3 16/16] platform/x86/intel/pmc: Show Die C6 counter on Meteor Lake David E. Box

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20231012023840.3845703-2-david.e.box@linux.intel.com \
    --to=david.e.box@linux.intel.com \
    --cc=ilpo.jarvinen@linux.intel.com \
    --cc=linux-kernel@vger.kernel.org \
    --cc=platform-driver-x86@vger.kernel.org \
    --cc=rajvi.jingar@linux.intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox