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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id n6-20020a05687104c600b001d6e9bb67d2sm388822oai.7.2023.10.17.12.28.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 12:29:02 -0700 (PDT) Received: (nullmailer pid 2548219 invoked by uid 1000); Tue, 17 Oct 2023 19:28:59 -0000 Date: Tue, 17 Oct 2023 14:28:59 -0500 From: Rob Herring To: Alvin =?utf-8?Q?=C5=A0ipraga?= Cc: Michael Turquette , Stephen Boyd , Krzysztof Kozlowski , Conor Dooley , Alvin =?utf-8?Q?=C5=A0ipraga?= , Sebastian Hesselbarth , Rabeeh Khoury , Jacob Siverskog , Sergej Sawazki , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v4 2/3] dt-bindings: clock: si5351: add PLL reset mode property Message-ID: <20231017192859.GA2544830-robh@kernel.org> References: <20231014-alvin-clk-si5351-no-pll-reset-v4-0-a3567024007d@bang-olufsen.dk> <20231014-alvin-clk-si5351-no-pll-reset-v4-2-a3567024007d@bang-olufsen.dk> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20231014-alvin-clk-si5351-no-pll-reset-v4-2-a3567024007d@bang-olufsen.dk> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, Oct 14, 2023 at 08:19:42PM +0200, Alvin Šipraga wrote: > From: Alvin Šipraga > > For applications where the PLL must be adjusted without glitches in the > clock output(s), a new silabs,pll-reset-mode property is added. It > can be used to specify whether or not the PLL should be reset after > adjustment. Resetting is known to cause glitches. > > For compatibility with older device trees, it must be assumed that the > default PLL reset mode is to unconditionally reset after adjustment. > > Cc: Sebastian Hesselbarth > Cc: Rabeeh Khoury > Cc: Jacob Siverskog > Cc: Sergej Sawazki > Signed-off-by: Alvin Šipraga > --- > .../devicetree/bindings/clock/silabs,si5351.yaml | 24 ++++++++++++++++++++++ > 1 file changed, 24 insertions(+) > > diff --git a/Documentation/devicetree/bindings/clock/silabs,si5351.yaml b/Documentation/devicetree/bindings/clock/silabs,si5351.yaml > index 16d1142c4a2f..9621b534f30e 100644 > --- a/Documentation/devicetree/bindings/clock/silabs,si5351.yaml > +++ b/Documentation/devicetree/bindings/clock/silabs,si5351.yaml > @@ -60,6 +60,27 @@ properties: > - description: PLL source, XTAL (0) or CLKIN (1, Si5351C only). > enum: [ 0, 1 ] > > + silabs,pll-reset-mode: > + $ref: /schemas/types.yaml#/definitions/uint32-matrix > + minItems: 1 If there's only 2 PLLs, then the maximum is 2 entries, right? So 'maxItems: 2' in addition. > + description: | Don't need '|' > + A list of cell pairs containing a PLL index and its reset mode. > + items: > + items: > + - description: PLL A (0) or PLL B (1) > + enum: [ 0, 1 ] > + - description: | > + Reset mode for the PLL. Mode can be one of: > + > + 0 - reset whenever PLL rate is adjusted (default mode) > + 1 - do not reset when PLL rate is adjusted > + > + In mode 1, the PLL is only reset if the silabs,pll-reset is > + specified in one of the clock output child nodes that also sources > + the PLL. This mode may be preferable if output clocks are expected > + to be adjusted without glitches. > + enum: [ 0, 1 ] > + > patternProperties: > "^clkout@[0-7]$": > type: object > @@ -199,6 +220,9 @@ examples: > /* Use XTAL input as source of PLL0 and PLL1 */ > silabs,pll-source = <0 0>, <1 0>; > > + /* Don't reset PLL1 on rate adjustment */ > + silabs,pll-reset-mode = <1 1>; > + > /* > * Overwrite CLK0 configuration with: > * - 8 mA output drive strength > > -- > 2.42.0 >