From: Thomas Gleixner <tglx@linutronix.de>
To: LKML <linux-kernel@vger.kernel.org>
Cc: x86@kernel.org, Borislav Petkov <bp@alien8.de>
Subject: [patch V5 27/39] x86/microcode: Handle "nosmt" correctly
Date: Tue, 17 Oct 2023 23:24:00 +0200 (CEST) [thread overview]
Message-ID: <20231017211723.465514319@linutronix.de> (raw)
In-Reply-To: 20231017200758.877560658@linutronix.de
From: Thomas Gleixner <tglx@linutronix.de>
On CPUs where microcode loading is not NMI-safe the SMT siblings which
are parked in one of the play_dead() variants still react to NMIs.
So if an NMI hits while the primary thread updates the microcode the
resulting behaviour is undefined. The default play_dead() implementation on
modern CPUs is using MWAIT which is not guaranteed to be safe against
a microcode update which affects MWAIT.
Take the cpus_booted_once_mask into account to detect this case and
refuse to load late if the vendor specific driver does not advertise
that late loading is NMI safe.
AMD stated that this is safe, so mark the AMD driver accordingly.
This requirement will be partially lifted in later changes.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
arch/x86/Kconfig | 2 -
arch/x86/kernel/cpu/microcode/amd.c | 9 +++--
arch/x86/kernel/cpu/microcode/core.c | 51 +++++++++++++++++++------------
arch/x86/kernel/cpu/microcode/internal.h | 13 +++----
4 files changed, 44 insertions(+), 31 deletions(-)
---
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -1320,7 +1320,7 @@ config MICROCODE_INITRD32
config MICROCODE_LATE_LOADING
bool "Late microcode loading (DANGEROUS)"
default n
- depends on MICROCODE
+ depends on MICROCODE && SMP
help
Loading microcode late, when the system is up and executing instructions
is a tricky business and should be avoided if possible. Just the sequence
--- a/arch/x86/kernel/cpu/microcode/amd.c
+++ b/arch/x86/kernel/cpu/microcode/amd.c
@@ -917,10 +917,11 @@ static void microcode_fini_cpu_amd(int c
}
static struct microcode_ops microcode_amd_ops = {
- .request_microcode_fw = request_microcode_amd,
- .collect_cpu_info = collect_cpu_info_amd,
- .apply_microcode = apply_microcode_amd,
- .microcode_fini_cpu = microcode_fini_cpu_amd,
+ .request_microcode_fw = request_microcode_amd,
+ .collect_cpu_info = collect_cpu_info_amd,
+ .apply_microcode = apply_microcode_amd,
+ .microcode_fini_cpu = microcode_fini_cpu_amd,
+ .nmi_safe = true,
};
struct microcode_ops * __init init_amd_microcode(void)
--- a/arch/x86/kernel/cpu/microcode/core.c
+++ b/arch/x86/kernel/cpu/microcode/core.c
@@ -254,23 +254,6 @@ static struct platform_device *microcode
*/
#define SPINUNIT 100 /* 100 nsec */
-static int check_online_cpus(void)
-{
- unsigned int cpu;
-
- /*
- * Make sure all CPUs are online. It's fine for SMT to be disabled if
- * all the primary threads are still online.
- */
- for_each_present_cpu(cpu) {
- if (topology_is_primary_thread(cpu) && !cpu_online(cpu)) {
- pr_err("Not all CPUs online, aborting microcode update.\n");
- return -EINVAL;
- }
- }
-
- return 0;
-}
static atomic_t late_cpus_in;
static atomic_t late_cpus_out;
@@ -387,6 +370,35 @@ static int microcode_reload_late(void)
return ret;
}
+/*
+ * Ensure that all required CPUs which are present and have been booted
+ * once are online.
+ *
+ * To pass this check, all primary threads must be online.
+ *
+ * If the microcode load is not safe against NMI then all SMT threads
+ * must be online as well because they still react to NMIs when they are
+ * soft-offlined and parked in one of the play_dead() variants. So if a
+ * NMI hits while the primary thread updates the microcode the resulting
+ * behaviour is undefined. The default play_dead() implementation on
+ * modern CPUs uses MWAIT, which is also not guaranteed to be safe
+ * against a microcode update which affects MWAIT.
+ */
+static bool ensure_cpus_are_online(void)
+{
+ unsigned int cpu;
+
+ for_each_cpu_and(cpu, cpu_present_mask, &cpus_booted_once_mask) {
+ if (!cpu_online(cpu)) {
+ if (topology_is_primary_thread(cpu) || !microcode_ops->nmi_safe) {
+ pr_err("CPU %u not online\n", cpu);
+ return false;
+ }
+ }
+ }
+ return true;
+}
+
static ssize_t reload_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t size)
@@ -402,9 +414,10 @@ static ssize_t reload_store(struct devic
cpus_read_lock();
- ret = check_online_cpus();
- if (ret)
+ if (!ensure_cpus_are_online()) {
+ ret = -EBUSY;
goto put;
+ }
tmp_ret = microcode_ops->request_microcode_fw(bsp, µcode_pdev->dev);
if (tmp_ret != UCODE_NEW)
--- a/arch/x86/kernel/cpu/microcode/internal.h
+++ b/arch/x86/kernel/cpu/microcode/internal.h
@@ -20,18 +20,17 @@ enum ucode_state {
struct microcode_ops {
enum ucode_state (*request_microcode_fw)(int cpu, struct device *dev);
-
void (*microcode_fini_cpu)(int cpu);
/*
- * The generic 'microcode_core' part guarantees that
- * the callbacks below run on a target cpu when they
- * are being called.
+ * The generic 'microcode_core' part guarantees that the callbacks
+ * below run on a target CPU when they are being called.
* See also the "Synchronization" section in microcode_core.c.
*/
- enum ucode_state (*apply_microcode)(int cpu);
- int (*collect_cpu_info)(int cpu, struct cpu_signature *csig);
- void (*finalize_late_load)(int result);
+ enum ucode_state (*apply_microcode)(int cpu);
+ int (*collect_cpu_info)(int cpu, struct cpu_signature *csig);
+ void (*finalize_late_load)(int result);
+ unsigned int nmi_safe : 1;
};
extern struct ucode_cpu_info ucode_cpu_info[];
next prev parent reply other threads:[~2023-10-17 21:25 UTC|newest]
Thread overview: 70+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-17 21:23 [patch V5 00/39] x86/microcode: Cleanup and late loading enhancements Thomas Gleixner
2023-10-17 21:23 ` [patch V5 01/39] x86/boot/32: Disable stackprotector and tracing for mk_early_pgtbl_32() Thomas Gleixner
2023-10-17 21:23 ` [patch V5 02/39] x86/boot: Use __pa_nodebug() in mk_early_pgtbl_32() Thomas Gleixner
2023-10-20 11:38 ` [tip: x86/microcode] " tip-bot2 for Thomas Gleixner
2023-10-17 21:23 ` [patch V5 03/39] x86/boot/32: De-uglify the 2/3 level paging difference " Thomas Gleixner
2023-10-18 10:00 ` Borislav Petkov
2023-10-18 13:20 ` Thomas Gleixner
2023-10-18 16:28 ` Borislav Petkov
2023-10-20 11:38 ` [tip: x86/microcode] " tip-bot2 for Thomas Gleixner
2023-10-17 21:23 ` [patch V5 04/39] x86/boot/32: Restructure mk_early_pgtbl_32() Thomas Gleixner
2023-10-20 11:38 ` [tip: x86/microcode] " tip-bot2 for Thomas Gleixner
2023-10-17 21:23 ` [patch V5 05/39] x86/microcode: Provide CONFIG_MICROCODE_INITRD32 Thomas Gleixner
2023-10-20 11:38 ` [tip: x86/microcode] " tip-bot2 for Thomas Gleixner
2023-10-17 21:23 ` [patch V5 06/39] x86/boot/32: Temporarily map initrd for microcode loading Thomas Gleixner
2023-10-20 11:38 ` [tip: x86/microcode] " tip-bot2 for Thomas Gleixner
2023-10-17 21:23 ` [patch V5 07/39] x86/microcode/32: Move early loading after paging enable Thomas Gleixner
2023-10-20 11:38 ` [tip: x86/microcode] " tip-bot2 for Thomas Gleixner
2023-10-17 21:23 ` [patch V5 08/39] x86/microcode/intel: Rip out mixed stepping support for Intel CPUs Thomas Gleixner
2023-10-20 11:38 ` [tip: x86/microcode] " tip-bot2 for Ashok Raj
2023-10-17 21:23 ` [patch V5 09/39] x86/microcode/intel: Simplify scan_microcode() Thomas Gleixner
2023-10-17 21:23 ` [patch V5 10/39] x86/microcode/intel: Simplify and rename generic_load_microcode() Thomas Gleixner
2023-10-17 21:23 ` [patch V5 11/39] x86/microcode/intel: Cleanup code further Thomas Gleixner
2023-10-17 21:23 ` [patch V5 12/39] x86/microcode/intel: Simplify early loading Thomas Gleixner
2023-10-20 11:38 ` [tip: x86/microcode] " tip-bot2 for Thomas Gleixner
2023-10-24 13:21 ` tip-bot2 for Thomas Gleixner
2023-10-17 21:23 ` [patch V5 13/39] x86/microcode/intel: Save the microcode only after a successful late-load Thomas Gleixner
2023-10-17 21:23 ` [patch V5 14/39] x86/microcode/intel: Switch to kvmalloc() Thomas Gleixner
2023-10-17 21:23 ` [patch V5 15/39] x86/microcode/intel: Unify microcode apply() functions Thomas Gleixner
2023-10-20 11:37 ` [tip: x86/microcode] " tip-bot2 for Thomas Gleixner
2023-10-24 13:21 ` tip-bot2 for Thomas Gleixner
2023-10-17 21:23 ` [patch V5 16/39] x86/microcode/intel: Rework intel_cpu_collect_info() Thomas Gleixner
2023-10-20 11:37 ` [tip: x86/microcode] " tip-bot2 for Thomas Gleixner
2023-10-24 13:21 ` tip-bot2 for Thomas Gleixner
2023-10-17 21:23 ` [patch V5 17/39] x86/microcode/intel: Reuse intel_cpu_collect_info() Thomas Gleixner
2023-10-17 21:23 ` [patch V5 18/39] x86/microcode/intel: Rework intel_find_matching_signature() Thomas Gleixner
2023-10-17 21:23 ` [patch V5 19/39] x86/microcode: Remove pointless apply() invocation Thomas Gleixner
2023-10-20 11:37 ` [tip: x86/microcode] " tip-bot2 for Thomas Gleixner
2023-10-24 13:21 ` tip-bot2 for Thomas Gleixner
2023-10-17 21:23 ` [patch V5 20/39] x86/microcode/amd: Use correct per CPU ucode_cpu_info Thomas Gleixner
2023-10-17 21:23 ` [patch V5 21/39] x86/microcode/amd: Cache builtin microcode too Thomas Gleixner
2023-10-17 21:23 ` [patch V5 22/39] x86/microcode/amd: Cache builtin/initrd microcode early Thomas Gleixner
2023-10-20 11:37 ` [tip: x86/microcode] " tip-bot2 for Thomas Gleixner
2023-10-24 13:21 ` tip-bot2 for Thomas Gleixner
2023-10-17 21:23 ` [patch V5 23/39] x86/microcode/amd: Use cached microcode for AP load Thomas Gleixner
2023-10-20 11:37 ` [tip: x86/microcode] " tip-bot2 for Thomas Gleixner
2023-10-24 13:21 ` tip-bot2 for Thomas Gleixner
2023-10-17 21:23 ` [patch V5 24/39] x86/microcode: Mop up early loading leftovers Thomas Gleixner
2023-10-20 11:37 ` [tip: x86/microcode] " tip-bot2 for Thomas Gleixner
2023-10-24 13:20 ` tip-bot2 for Thomas Gleixner
2023-10-17 21:23 ` [patch V5 25/39] x86/microcode: Get rid of the schedule work indirection Thomas Gleixner
2023-10-20 11:37 ` [tip: x86/microcode] " tip-bot2 for Thomas Gleixner
2023-10-24 13:20 ` tip-bot2 for Thomas Gleixner
2023-10-17 21:23 ` [patch V5 26/39] x86/microcode: Clean up mc_cpu_down_prep() Thomas Gleixner
2023-10-17 21:24 ` Thomas Gleixner [this message]
2023-10-17 21:24 ` [patch V5 28/39] x86/microcode: Clarify the late load logic Thomas Gleixner
2023-10-17 21:24 ` [patch V5 29/39] x86/microcode: Sanitize __wait_for_cpus() Thomas Gleixner
2023-10-17 21:24 ` [patch V5 30/39] x86/microcode: Add per CPU result state Thomas Gleixner
2023-10-20 11:37 ` [tip: x86/microcode] " tip-bot2 for Thomas Gleixner
2023-10-24 13:20 ` tip-bot2 for Thomas Gleixner
2023-10-17 21:24 ` [patch V5 31/39] x86/microcode: Add per CPU control field Thomas Gleixner
2023-10-17 21:24 ` [patch V5 32/39] x86/microcode: Provide new control functions Thomas Gleixner
2023-10-17 21:24 ` [patch V5 33/39] x86/microcode: Replace the all-in-one rendevous handler Thomas Gleixner
2023-10-17 21:24 ` [patch V5 34/39] x86/microcode: Rendezvous and load in NMI Thomas Gleixner
2023-10-17 21:24 ` [patch V5 35/39] x86/microcode: Protect against instrumentation Thomas Gleixner
2023-10-17 21:24 ` [patch V5 36/39] x86/apic: Provide apic_force_nmi_on_cpu() Thomas Gleixner
2023-10-17 21:24 ` [patch V5 37/39] x86/microcode: Handle "offline" CPUs correctly Thomas Gleixner
2023-10-17 21:24 ` [patch V5 38/39] x86/microcode: Prepare for minimal revision check Thomas Gleixner
2023-10-20 11:37 ` [tip: x86/microcode] " tip-bot2 for Thomas Gleixner
2023-10-24 13:20 ` tip-bot2 for Thomas Gleixner
2023-10-17 21:24 ` [patch V5 39/39] x86/microcode/intel: Add a minimum required revision for late loading Thomas Gleixner
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20231017211723.465514319@linutronix.de \
--to=tglx@linutronix.de \
--cc=bp@alien8.de \
--cc=linux-kernel@vger.kernel.org \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox