Re: [PATCH v2] PCI: keystone: Fix ks_pcie_v3_65_add_bus() for AM654x SoC

Siddharth Vadapalli
2023-10-18T08:24:39Z

Ravi,

On 18/10/23 13:49, Ravi Gunasekaran wrote:
> Siddharth,
>
>
> On 10/18/23 1:20 PM, Siddharth Vadapalli wrote:
>> The ks_pcie_v3_65_add_bus() member of "ks_pcie_ops" was added for
>> platforms using DW PCIe IP-core version 3.65a. The AM654x SoC uses
>> DW PCIe IP-core version 4.90a and ks_pcie_v3_65_add_bus() is not
>> applicable to it.
>>
>> The commit which added support for the AM654x SoC has reused majority
>> of the functions with the help of the "is_am6" flag to handle AM654x
>> separately where applicable. Thus, make use of the "is_am6" flag and
>> change ks_pcie_v3_65_add_bus() to no-op for AM654x SoC.
>>
>> Fixes: 18b0415bc802 ("PCI: keystone: Add support for PCIe RC in AM654x Platforms")
>
> 6ab15b5e7057 (PCI: dwc: keystone: Convert .scan_bus() callback to use add_bus)
> is that one that seems to have introduced this issue.
>
> ks_pcie_v3_65_scan_bus() was for IP version 3.65 and this was renamed and
> added to "ks_pcie_ops" which is used by other IP versions as well.

Thank you for reviewing the patch and pointing this out. I will update the
commit message with the correct Fixes tag as well as the appropriate description
and post the v3 patch if there is no further feedback from others on this patch.

>
>
>> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
>> ---
>> Hello,
>>
>> This patch is based on linux-next tagged next-20231018.
>>
>> The v1 of this patch is at:
>> https://lore.kernel.org/r/20231011123451.34827-1-s-vadapalli@ti.com/

...

>> return 0;
>>
>> /* Configure and set up BAR0 */
>

--
Regards,
Siddharth.