From: Xu Lu <luxu.kernel@bytedance.com>
To: paul.walmsley@sifive.com, palmer@dabbelt.com,
aou@eecs.berkeley.edu, tglx@linutronix.de, maz@kernel.org,
anup@brainfault.org, atishp@atishpatra.org
Cc: dengliang.1214@bytedance.com, liyu.yukiteru@bytedance.com,
sunjiadong.lff@bytedance.com, xieyongji@bytedance.com,
lihangjing@bytedance.com, chaiwen.cc@bytedance.com,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
Xu Lu <luxu.kernel@bytedance.com>
Subject: [RFC 01/12] riscv: Introduce CONFIG_RISCV_PSEUDO_NMI
Date: Mon, 23 Oct 2023 16:29:00 +0800 [thread overview]
Message-ID: <20231023082911.23242-2-luxu.kernel@bytedance.com> (raw)
In-Reply-To: <20231023082911.23242-1-luxu.kernel@bytedance.com>
This commit introduces a new config RISCV_PSEUDO_NMI to control
whether enabling the pseudo NMI feature on RISC-V.
Signed-off-by: Xu Lu <luxu.kernel@bytedance.com>
---
arch/riscv/Kconfig | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index d607ab0f7c6d..487e4293f31e 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -669,6 +669,16 @@ config RISCV_BOOT_SPINWAIT
If unsure what to do here, say N.
+config RISCV_PSEUDO_NMI
+ bool "Support for NMI-like interrupts"
+ depends on !RISCV_M_MODE
+ default n
+ help
+ Adds support for mimicking Non-Maskable Interrupts through the use of
+ CSR_IE register.
+
+ If unsure, say N.
+
config ARCH_SUPPORTS_KEXEC
def_bool MMU
--
2.20.1
next prev parent reply other threads:[~2023-10-23 8:29 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-23 8:28 [RFC 00/12] riscv: Introduce Pseudo NMI Xu Lu
2023-10-23 8:29 ` Xu Lu [this message]
2023-10-23 8:29 ` [RFC 02/12] riscv: Make CSR_IE register part of context Xu Lu
2023-10-23 8:29 ` [RFC 03/12] riscv: Switch to CSR_IE masking when disabling irqs Xu Lu
2023-10-23 8:29 ` [RFC 04/12] riscv: Switch back to CSR_STATUS masking when going idle Xu Lu
2023-10-23 8:29 ` [RFC 05/12] riscv: kvm: Switch back to CSR_STATUS masking when entering guest Xu Lu
2023-10-23 8:29 ` [RFC 06/12] riscv: Allow requesting irq as pseudo NMI Xu Lu
2023-10-23 8:29 ` [RFC 07/12] riscv: Handle pseudo NMI in arch irq handler Xu Lu
2023-10-23 8:29 ` [RFC 08/12] riscv: Enable NMIs during irqs disabled context Xu Lu
2023-10-23 8:29 ` [RFC 09/12] riscv: Enable NMIs during exceptions Xu Lu
2023-10-23 8:29 ` [RFC 10/12] riscv: Enable NMIs during interrupt handling Xu Lu
2023-10-23 8:29 ` [RFC 11/12] riscv: Request pmu overflow interrupt as NMI Xu Lu
2023-10-23 8:29 ` [RFC 12/12] riscv: Enable CONFIG_RISCV_PSEUDO_NMI in default Xu Lu
2023-10-25 23:01 ` [RFC 00/12] riscv: Introduce Pseudo NMI Atish Patra
2023-10-26 13:56 ` [External] " Xu Lu
2023-10-26 19:41 ` Atish Patra
2023-10-27 7:33 ` Xu Lu
2023-10-27 7:55 ` Thomas Gleixner
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