From: Anup Patel <apatel@ventanamicro.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Thomas Gleixner <tglx@linutronix.de>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Frank Rowand <frowand.list@gmail.com>
Cc: "Conor Dooley" <conor+dt@kernel.org>,
"Marc Zyngier" <maz@kernel.org>, "Björn Töpel" <bjorn@kernel.org>,
"Atish Patra" <atishp@atishpatra.org>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Sunil V L" <sunilvl@ventanamicro.com>,
"Saravana Kannan" <saravanak@google.com>,
"Anup Patel" <anup@brainfault.org>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org,
"Anup Patel" <apatel@ventanamicro.com>
Subject: [PATCH 0/3] Linux RISC-V AIA Preparatory Series
Date: Wed, 25 Oct 2023 19:58:17 +0530 [thread overview]
Message-ID: <20231025142820.390238-1-apatel@ventanamicro.com> (raw)
The first three patches of the v11 Linux RISC-V AIA series can be
merged independently hence sending these patches as an independent
perparatory series.
(Refer, https://www.spinics.net/lists/devicetree/msg643764.html)
These patches can also be found in the riscv_aia_prep_v1 branch at:
https://github.com/avpatel/linux.git
Anup Patel (3):
RISC-V: Don't fail in riscv_of_parent_hartid() for disabled HARTs
of: property: Add fw_devlink support for msi-parent
irqchip/sifive-plic: Fix syscore registration for multi-socket systems
arch/riscv/kernel/cpu.c | 11 ++++++-----
drivers/irqchip/irq-sifive-plic.c | 7 ++++---
drivers/of/property.c | 2 ++
3 files changed, 12 insertions(+), 8 deletions(-)
--
2.34.1
next reply other threads:[~2023-10-25 14:28 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-25 14:28 Anup Patel [this message]
2023-10-25 14:28 ` [PATCH 1/3] RISC-V: Don't fail in riscv_of_parent_hartid() for disabled HARTs Anup Patel
2023-10-27 7:59 ` Thomas Gleixner
2023-10-25 14:28 ` [PATCH 2/3] of: property: Add fw_devlink support for msi-parent Anup Patel
2023-10-27 7:57 ` Thomas Gleixner
[not found] ` <CAK9=C2VRNJGySLT8_oN=U9Pe9C9mOdPjOUr24ugXciT0Hx9pqA@mail.gmail.com>
2023-10-27 17:29 ` Thomas Gleixner
2023-10-25 14:28 ` [PATCH 3/3] irqchip/sifive-plic: Fix syscore registration for multi-socket systems Anup Patel
2023-10-27 8:17 ` [tip: irq/core] " tip-bot2 for Anup Patel
2023-10-25 14:31 ` [PATCH 0/3] Linux RISC-V AIA Preparatory Series Anup Patel
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