From: Anup Patel <apatel@ventanamicro.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Thomas Gleixner <tglx@linutronix.de>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Frank Rowand <frowand.list@gmail.com>
Cc: "Conor Dooley" <conor+dt@kernel.org>,
"Marc Zyngier" <maz@kernel.org>, "Björn Töpel" <bjorn@kernel.org>,
"Atish Patra" <atishp@atishpatra.org>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Sunil V L" <sunilvl@ventanamicro.com>,
"Saravana Kannan" <saravanak@google.com>,
"Anup Patel" <anup@brainfault.org>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org,
"Anup Patel" <apatel@ventanamicro.com>
Subject: [PATCH 3/3] irqchip/sifive-plic: Fix syscore registration for multi-socket systems
Date: Wed, 25 Oct 2023 19:58:20 +0530 [thread overview]
Message-ID: <20231025142820.390238-4-apatel@ventanamicro.com> (raw)
In-Reply-To: <20231025142820.390238-1-apatel@ventanamicro.com>
On multi-socket systems, we will have a separate PLIC in each socket
so we should register syscore operation only once for multi-socket
systems.
Fixes: e80f0b6a2cf3 ("irqchip/irq-sifive-plic: Add syscore callbacks for hibernation")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
drivers/irqchip/irq-sifive-plic.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
index e1484905b7bd..5b7bc4fd9517 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -532,17 +532,18 @@ static int __init __plic_init(struct device_node *node,
}
/*
- * We can have multiple PLIC instances so setup cpuhp state only
- * when context handler for current/boot CPU is present.
+ * We can have multiple PLIC instances so setup cpuhp state
+ * and register syscore operations only when context handler
+ * for current/boot CPU is present.
*/
handler = this_cpu_ptr(&plic_handlers);
if (handler->present && !plic_cpuhp_setup_done) {
cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING,
"irqchip/sifive/plic:starting",
plic_starting_cpu, plic_dying_cpu);
+ register_syscore_ops(&plic_irq_syscore_ops);
plic_cpuhp_setup_done = true;
}
- register_syscore_ops(&plic_irq_syscore_ops);
pr_info("%pOFP: mapped %d interrupts with %d handlers for"
" %d contexts.\n", node, nr_irqs, nr_handlers, nr_contexts);
--
2.34.1
next prev parent reply other threads:[~2023-10-25 14:39 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-25 14:28 [PATCH 0/3] Linux RISC-V AIA Preparatory Series Anup Patel
2023-10-25 14:28 ` [PATCH 1/3] RISC-V: Don't fail in riscv_of_parent_hartid() for disabled HARTs Anup Patel
2023-10-27 7:59 ` Thomas Gleixner
2023-10-25 14:28 ` [PATCH 2/3] of: property: Add fw_devlink support for msi-parent Anup Patel
2023-10-27 7:57 ` Thomas Gleixner
[not found] ` <CAK9=C2VRNJGySLT8_oN=U9Pe9C9mOdPjOUr24ugXciT0Hx9pqA@mail.gmail.com>
2023-10-27 17:29 ` Thomas Gleixner
2023-10-25 14:28 ` Anup Patel [this message]
2023-10-27 8:17 ` [tip: irq/core] irqchip/sifive-plic: Fix syscore registration for multi-socket systems tip-bot2 for Anup Patel
2023-10-25 14:31 ` [PATCH 0/3] Linux RISC-V AIA Preparatory Series Anup Patel
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