From: Paz Zcharya <pazz@chromium.org>
To: Jani Nikula <jani.nikula@linux.intel.com>,
Joonas Lahtinen <joonas.lahtinen@linux.intel.com>,
Rodrigo Vivi <rodrigo.vivi@intel.com>,
Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: "Subrata Banik" <subratabanik@google.com>,
"Drew Davenport" <ddavenport@chromium.org>,
"Sean Paul" <seanpaul@chromium.org>,
"Manasi Navare" <navaremanasi@chromium.org>,
"Paz Zcharya" <pazz@chromium.org>,
"Paz Zcharya" <pazz@google.com>,
"Andrzej Hajda" <andrzej.hajda@intel.com>,
"Ankit Nautiyal" <ankit.k.nautiyal@intel.com>,
"Daniel Vetter" <daniel@ffwll.ch>,
"David Airlie" <airlied@gmail.com>,
"José Roberto de Souza" <jose.souza@intel.com>,
"Jouni Högander" <jouni.hogander@intel.com>,
"Khaled Almahallawy" <khaled.almahallawy@intel.com>,
"Luca Coelho" <luciano.coelho@intel.com>,
"Matt Roper" <matthew.d.roper@intel.com>,
"Mika Kahola" <mika.kahola@intel.com>,
"Stanislav Lisovskiy" <stanislav.lisovskiy@intel.com>,
"Suraj Kandpal" <suraj.kandpal@intel.com>,
"Uma Shankar" <uma.shankar@intel.com>,
"Ville Syrjälä" <ville.syrjala@linux.intel.com>,
dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org,
linux-kernel@vger.kernel.org
Subject: [PATCH] drm/i915/display: Only fail fastset on PSR2
Date: Tue, 31 Oct 2023 23:21:57 +0000 [thread overview]
Message-ID: <20231031232245.1331194-1-pazz@google.com> (raw)
Currently, i915 fails fastset if both the sink and the source support
any version of PSR and regardless of the configuration setting of the
driver (i.e., i915.enable_psr kernel argument). However, the
implementation of PSR1 enable sequence is already seamless
and works smoothly with fastset. Accordingly, do not fail fastset
if PSR2 is not enabled.
Signed-off-by: Paz Zcharya <pazz@google.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 4 ++--
drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
drivers/gpu/drm/i915/display/intel_psr.h | 1 +
3 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index e0e4cb529284..a1af96e31518 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2584,8 +2584,8 @@ bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
fastset = false;
}
- if (CAN_PSR(intel_dp)) {
- drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute PSR state\n",
+ if (CAN_PSR(intel_dp) && psr2_global_enabled(intel_dp)) {
+ drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to PSR2\n",
encoder->base.base.id, encoder->base.name);
crtc_state->uapi.mode_changed = true;
fastset = false;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 97d5eef10130..388bc3246db9 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -187,7 +187,7 @@ static bool psr_global_enabled(struct intel_dp *intel_dp)
}
}
-static bool psr2_global_enabled(struct intel_dp *intel_dp)
+bool psr2_global_enabled(struct intel_dp *intel_dp)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 0b95e8aa615f..6f3c36389cd3 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -21,6 +21,7 @@ struct intel_encoder;
struct intel_plane;
struct intel_plane_state;
+bool psr2_global_enabled(struct intel_dp *intel_dp);
void intel_psr_init_dpcd(struct intel_dp *intel_dp);
void intel_psr_pre_plane_update(struct intel_atomic_state *state,
struct intel_crtc *crtc);
--
2.42.0.820.g83a721a137-goog
next reply other threads:[~2023-10-31 23:23 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-31 23:21 Paz Zcharya [this message]
2023-11-01 6:26 ` [PATCH] drm/i915/display: Only fail fastset on PSR2 Hogander, Jouni
2023-11-01 15:45 ` Paz Zcharya
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