* [PATCH 0/2] Change the sg2042 timer layout to fit aclint format
@ 2023-11-13 2:22 Inochi Amaoto
2023-11-13 2:23 ` [PATCH 1/2] dt-bindings: timer: thead,c900-aclint-mtimer: separate mtime and mtimecmp regs Inochi Amaoto
2023-11-13 2:24 ` [PATCH 2/2] riscv: dts: sophgo: separate sg2042 mtime and mtimecmp to fit aclint format Inochi Amaoto
0 siblings, 2 replies; 4+ messages in thread
From: Inochi Amaoto @ 2023-11-13 2:22 UTC (permalink / raw)
To: Guo Ren, Jisheng Zhang, Daniel Lezcano, Thomas Gleixner,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Chao Wei,
Chen Wang, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Inochi Amaoto
Cc: linux-kernel, devicetree, linux-riscv
As the sg2042 uses different address for timer and mswi of its clint
device, it should follow the aclint format. For the previous patchs,
it only use only one address for both mtime and mtimer, this is can
not be parsed by OpenSBI. To resolve this, separate these two registers
in the dtb.
Link: https://lists.infradead.org/pipermail/opensbi/2023-October/005693.html
Link: https://lists.infradead.org/pipermail/opensbi/2023-October/005738.html
Link: https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc
Inochi Amaoto (2):
dt-bindings: timer: thead,c900-aclint-mtimer: separate mtime and
mtimecmp regs
riscv: dts: sophgo: separate sg2042 mtime and mtimecmp to fit aclint
format
.../timer/thead,c900-aclint-mtimer.yaml | 5 +-
arch/riscv/boot/dts/sophgo/sg2042.dtsi | 80 +++++++++++--------
2 files changed, 51 insertions(+), 34 deletions(-)
--
2.42.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 1/2] dt-bindings: timer: thead,c900-aclint-mtimer: separate mtime and mtimecmp regs
2023-11-13 2:22 [PATCH 0/2] Change the sg2042 timer layout to fit aclint format Inochi Amaoto
@ 2023-11-13 2:23 ` Inochi Amaoto
2023-11-13 13:18 ` Conor Dooley
2023-11-13 2:24 ` [PATCH 2/2] riscv: dts: sophgo: separate sg2042 mtime and mtimecmp to fit aclint format Inochi Amaoto
1 sibling, 1 reply; 4+ messages in thread
From: Inochi Amaoto @ 2023-11-13 2:23 UTC (permalink / raw)
To: Guo Ren, Jisheng Zhang, Daniel Lezcano, Thomas Gleixner,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Inochi Amaoto, Chen Wang
Cc: linux-kernel, devicetree, linux-riscv
To make thead aclint timer more closer to the aclint spec, use two regs
to represent the mtime and mtimecmp.
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Fixes: 4734449f7311 ("dt-bindings: timer: Add Sophgo sg2042 CLINT timer")
Link: https://lists.infradead.org/pipermail/opensbi/2023-October/005693.html
Link: https://lists.infradead.org/pipermail/opensbi/2023-October/005738.html
Link: https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc
---
.../devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml b/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml
index fbd235650e52..c3080962d902 100644
--- a/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml
+++ b/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml
@@ -17,7 +17,7 @@ properties:
- const: thead,c900-aclint-mtimer
reg:
- maxItems: 1
+ maxItems: 2
interrupts-extended:
minItems: 1
@@ -38,6 +38,7 @@ examples:
<&cpu2intc 7>,
<&cpu3intc 7>,
<&cpu4intc 7>;
- reg = <0xac000000 0x00010000>;
+ reg = <0xac000000 0x00000000>,
+ <0xac000000 0x0000c000>;
};
...
--
2.42.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/2] riscv: dts: sophgo: separate sg2042 mtime and mtimecmp to fit aclint format
2023-11-13 2:22 [PATCH 0/2] Change the sg2042 timer layout to fit aclint format Inochi Amaoto
2023-11-13 2:23 ` [PATCH 1/2] dt-bindings: timer: thead,c900-aclint-mtimer: separate mtime and mtimecmp regs Inochi Amaoto
@ 2023-11-13 2:24 ` Inochi Amaoto
1 sibling, 0 replies; 4+ messages in thread
From: Inochi Amaoto @ 2023-11-13 2:24 UTC (permalink / raw)
To: Guo Ren, Jisheng Zhang, Chao Wei, Chen Wang, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Inochi Amaoto, Xiaoguang Xing
Cc: devicetree, linux-riscv, linux-kernel
Change the timer layout in the dtb to fit the format that needed by
the SBI.
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Fixes: 967a94a92aaa ("riscv: dts: add initial Sophgo SG2042 SoC device tree")
---
arch/riscv/boot/dts/sophgo/sg2042.dtsi | 80 +++++++++++++++-----------
1 file changed, 48 insertions(+), 32 deletions(-)
diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
index 93256540d078..0b5d93b5c783 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
@@ -93,144 +93,160 @@ clint_mswi: interrupt-controller@7094000000 {
<&cpu63_intc 3>;
};
- clint_mtimer0: timer@70ac000000 {
+ clint_mtimer0: timer@70ac004000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac000000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac004000 0x00000000 0x00000000>,
+ <0x00000070 0xac004000 0x00000000 0x0000c000>;
interrupts-extended = <&cpu0_intc 7>,
<&cpu1_intc 7>,
<&cpu2_intc 7>,
<&cpu3_intc 7>;
};
- clint_mtimer1: timer@70ac010000 {
+ clint_mtimer1: timer@70ac014000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac010000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac014000 0x00000000 0x00000000>,
+ <0x00000070 0xac014000 0x00000000 0x0000c000>;
interrupts-extended = <&cpu4_intc 7>,
<&cpu5_intc 7>,
<&cpu6_intc 7>,
<&cpu7_intc 7>;
};
- clint_mtimer2: timer@70ac020000 {
+ clint_mtimer2: timer@70ac024000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac020000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac024000 0x00000000 0x00000000>,
+ <0x00000070 0xac024000 0x00000000 0x0000c000>;
interrupts-extended = <&cpu8_intc 7>,
<&cpu9_intc 7>,
<&cpu10_intc 7>,
<&cpu11_intc 7>;
};
- clint_mtimer3: timer@70ac030000 {
+ clint_mtimer3: timer@70ac034000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac030000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac034000 0x00000000 0x00000000>,
+ <0x00000070 0xac034000 0x00000000 0x0000c000>;
interrupts-extended = <&cpu12_intc 7>,
<&cpu13_intc 7>,
<&cpu14_intc 7>,
<&cpu15_intc 7>;
};
- clint_mtimer4: timer@70ac040000 {
+ clint_mtimer4: timer@70ac044000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac040000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac044000 0x00000000 0x00000000>,
+ <0x00000070 0xac044000 0x00000000 0x0000c000>;
interrupts-extended = <&cpu16_intc 7>,
<&cpu17_intc 7>,
<&cpu18_intc 7>,
<&cpu19_intc 7>;
};
- clint_mtimer5: timer@70ac050000 {
+ clint_mtimer5: timer@70ac054000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac050000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac054000 0x00000000 0x00000000>,
+ <0x00000070 0xac054000 0x00000000 0x0000c000>;
interrupts-extended = <&cpu20_intc 7>,
<&cpu21_intc 7>,
<&cpu22_intc 7>,
<&cpu23_intc 7>;
};
- clint_mtimer6: timer@70ac060000 {
+ clint_mtimer6: timer@70ac064000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac060000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac064000 0x00000000 0x00000000>,
+ <0x00000070 0xac064000 0x00000000 0x0000c000>;
interrupts-extended = <&cpu24_intc 7>,
<&cpu25_intc 7>,
<&cpu26_intc 7>,
<&cpu27_intc 7>;
};
- clint_mtimer7: timer@70ac070000 {
+ clint_mtimer7: timer@70ac074000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac070000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac074000 0x00000000 0x00000000>,
+ <0x00000070 0xac074000 0x00000000 0x0000c000>;
interrupts-extended = <&cpu28_intc 7>,
<&cpu29_intc 7>,
<&cpu30_intc 7>,
<&cpu31_intc 7>;
};
- clint_mtimer8: timer@70ac080000 {
+ clint_mtimer8: timer@70ac084000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac080000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac084000 0x00000000 0x00000000>,
+ <0x00000070 0xac084000 0x00000000 0x0000c000>;
interrupts-extended = <&cpu32_intc 7>,
<&cpu33_intc 7>,
<&cpu34_intc 7>,
<&cpu35_intc 7>;
};
- clint_mtimer9: timer@70ac090000 {
+ clint_mtimer9: timer@70ac094000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac090000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac094000 0x00000000 0x00000000>,
+ <0x00000070 0xac094000 0x00000000 0x0000c000>;
interrupts-extended = <&cpu36_intc 7>,
<&cpu37_intc 7>,
<&cpu38_intc 7>,
<&cpu39_intc 7>;
};
- clint_mtimer10: timer@70ac0a0000 {
+ clint_mtimer10: timer@70ac0a4000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac0a0000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac0a4000 0x00000000 0x00000000>,
+ <0x00000070 0xac0a4000 0x00000000 0x0000c000>;
interrupts-extended = <&cpu40_intc 7>,
<&cpu41_intc 7>,
<&cpu42_intc 7>,
<&cpu43_intc 7>;
};
- clint_mtimer11: timer@70ac0b0000 {
+ clint_mtimer11: timer@70ac0b4000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac0b0000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac0b4000 0x00000000 0x00000000>,
+ <0x00000070 0xac0b4000 0x00000000 0x0000c000>;
interrupts-extended = <&cpu44_intc 7>,
<&cpu45_intc 7>,
<&cpu46_intc 7>,
<&cpu47_intc 7>;
};
- clint_mtimer12: timer@70ac0c0000 {
+ clint_mtimer12: timer@70ac0c4000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac0c0000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac0c4000 0x00000000 0x00000000>,
+ <0x00000070 0xac0c4000 0x00000000 0x0000c000>;
interrupts-extended = <&cpu48_intc 7>,
<&cpu49_intc 7>,
<&cpu50_intc 7>,
<&cpu51_intc 7>;
};
- clint_mtimer13: timer@70ac0d0000 {
+ clint_mtimer13: timer@70ac0d4000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac0d0000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac0d4000 0x00000000 0x00000000>,
+ <0x00000070 0xac0d4000 0x00000000 0x0000c000>;
interrupts-extended = <&cpu52_intc 7>,
<&cpu53_intc 7>,
<&cpu54_intc 7>,
<&cpu55_intc 7>;
};
- clint_mtimer14: timer@70ac0e0000 {
+ clint_mtimer14: timer@70ac0e4000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac0e0000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac0e4000 0x00000000 0x00000000>,
+ <0x00000070 0xac0e4000 0x00000000 0x0000c000>;
interrupts-extended = <&cpu56_intc 7>,
<&cpu57_intc 7>,
<&cpu58_intc 7>,
<&cpu59_intc 7>;
};
- clint_mtimer15: timer@70ac0f0000 {
+ clint_mtimer15: timer@70ac0f4000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac0f0000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac0f4000 0x00000000 0x00000000>,
+ <0x00000070 0xac0f4000 0x00000000 0x0000c000>;
interrupts-extended = <&cpu60_intc 7>,
<&cpu61_intc 7>,
<&cpu62_intc 7>,
--
2.42.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 1/2] dt-bindings: timer: thead,c900-aclint-mtimer: separate mtime and mtimecmp regs
2023-11-13 2:23 ` [PATCH 1/2] dt-bindings: timer: thead,c900-aclint-mtimer: separate mtime and mtimecmp regs Inochi Amaoto
@ 2023-11-13 13:18 ` Conor Dooley
0 siblings, 0 replies; 4+ messages in thread
From: Conor Dooley @ 2023-11-13 13:18 UTC (permalink / raw)
To: Inochi Amaoto
Cc: Guo Ren, Jisheng Zhang, Daniel Lezcano, Thomas Gleixner,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Chen Wang, linux-kernel, devicetree,
linux-riscv
[-- Attachment #1: Type: text/plain, Size: 2131 bytes --]
On Mon, Nov 13, 2023 at 10:23:59AM +0800, Inochi Amaoto wrote:
> To make thead aclint timer more closer to the aclint spec, use two regs
> to represent the mtime and mtimecmp.
In the devicetree patch you say:
"Change the timer layout in the dtb to fit the format that needed by
the SBI."
That seems like a far more important thing to say in the binding patch,
since that is where the ABI is set. You also provide two links to
discussion on the mailing list for opensbi, but provide no context in
the commit message here for why they're relevant. The 005738 one doesn't
seem to be relevant at all?
Could you please resubmit this with a better commit message that
explains why the ABI here needs to change?
Thanks,
Conor.
>
> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> Fixes: 4734449f7311 ("dt-bindings: timer: Add Sophgo sg2042 CLINT timer")
> Link: https://lists.infradead.org/pipermail/opensbi/2023-October/005693.html
> Link: https://lists.infradead.org/pipermail/opensbi/2023-October/005738.html
> Link: https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc
> ---
> .../devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml b/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml
> index fbd235650e52..c3080962d902 100644
> --- a/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml
> +++ b/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml
> @@ -17,7 +17,7 @@ properties:
> - const: thead,c900-aclint-mtimer
>
> reg:
> - maxItems: 1
> + maxItems: 2
>
> interrupts-extended:
> minItems: 1
> @@ -38,6 +38,7 @@ examples:
> <&cpu2intc 7>,
> <&cpu3intc 7>,
> <&cpu4intc 7>;
> - reg = <0xac000000 0x00010000>;
> + reg = <0xac000000 0x00000000>,
> + <0xac000000 0x0000c000>;
> };
> ...
> --
> 2.42.1
>
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2023-11-13 2:22 [PATCH 0/2] Change the sg2042 timer layout to fit aclint format Inochi Amaoto
2023-11-13 2:23 ` [PATCH 1/2] dt-bindings: timer: thead,c900-aclint-mtimer: separate mtime and mtimecmp regs Inochi Amaoto
2023-11-13 13:18 ` Conor Dooley
2023-11-13 2:24 ` [PATCH 2/2] riscv: dts: sophgo: separate sg2042 mtime and mtimecmp to fit aclint format Inochi Amaoto
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