[PATCH 0/3] clk: meson: add MIPI ISP & CSI PHY clocks

[PATCH 0/3] clk: meson: add MIPI ISP & CSI PHY clocks

[Neil Armstrong]

Add MIPI ISP & CSI PHY clock bindings and entries for
the Amlogic G12B SoC.

Based on the CTS_ENCL clock bindings patch at [1]

[1] https://lore.kernel.org/all/20231109-amlogic-v6-4-upstream-dsi-ccf-vim3-v8-1-81e4aeeda193@linaro.org/

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
Neil Armstrong (3):
      dt-bindings: clock: g12a-clkc: add MIPI ISP & CSI PHY clock ids
      clk: meson: g12a: add MIPI ISP clocks
      clk: meson: g12a: add CSI & ISP gates clocks

 drivers/clk/meson/g12a.c              | 75 +++++++++++++++++++++++++++++++++++
 drivers/clk/meson/g12a.h              |  1 +
 include/dt-bindings/clock/g12a-clkc.h |  6 +++
 3 files changed, 82 insertions(+)
---
base-commit: 71ea46af56818a97cb5ea5d6554a0f10ea624d6d
change-id: 20231114-topic-amlogic-upstream-isp-clocks-aa2859a633f0

Best regards,
-- 
Neil Armstrong <neil.armstrong@linaro.org>

[PATCH 1/3] dt-bindings: clock: g12a-clkc: add MIPI ISP & CSI PHY clock ids

[Neil Armstrong]

Add MIPI ISP & CSI PHY clock ids to G12A clock bindings header

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
 include/dt-bindings/clock/g12a-clkc.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h
index 636d713f95ff..fd09819da2ec 100644
--- a/include/dt-bindings/clock/g12a-clkc.h
+++ b/include/dt-bindings/clock/g12a-clkc.h
@@ -281,5 +281,11 @@
 #define CLKID_MIPI_DSI_PXCLK			270
 #define CLKID_CTS_ENCL				271
 #define CLKID_CTS_ENCL_SEL			272
+#define CLKID_MIPI_ISP_DIV			273
+#define CLKID_MIPI_ISP_SEL			274
+#define CLKID_MIPI_ISP				275
+#define CLKID_MIPI_ISP_GATE			276
+#define CLKID_MIPI_ISP_CSI_PHY0			277
+#define CLKID_MIPI_ISP_CSI_PHY1			278
 
 #endif /* __G12A_CLKC_H */

-- 
2.34.1

Re: [PATCH 1/3] dt-bindings: clock: g12a-clkc: add MIPI ISP & CSI PHY clock ids

[Conor Dooley]

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On Tue, Nov 14, 2023 at 11:14:43AM +0100, Neil Armstrong wrote:
> Add MIPI ISP & CSI PHY clock ids to G12A clock bindings header
> 
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

Cheers,
Conor,

> ---
>  include/dt-bindings/clock/g12a-clkc.h | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h
> index 636d713f95ff..fd09819da2ec 100644
> --- a/include/dt-bindings/clock/g12a-clkc.h
> +++ b/include/dt-bindings/clock/g12a-clkc.h
> @@ -281,5 +281,11 @@
>  #define CLKID_MIPI_DSI_PXCLK			270
>  #define CLKID_CTS_ENCL				271
>  #define CLKID_CTS_ENCL_SEL			272
> +#define CLKID_MIPI_ISP_DIV			273
> +#define CLKID_MIPI_ISP_SEL			274
> +#define CLKID_MIPI_ISP				275
> +#define CLKID_MIPI_ISP_GATE			276
> +#define CLKID_MIPI_ISP_CSI_PHY0			277
> +#define CLKID_MIPI_ISP_CSI_PHY1			278
>  
>  #endif /* __G12A_CLKC_H */
> 
> -- 
> 2.34.1
> 

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[PATCH 2/3] clk: meson: g12a: add MIPI ISP clocks

[Neil Armstrong]

Add the MIPI ISP gate, divider and mux used to feed the MIPI CSI ISP
(Image Signal Processor) IP on the Amlogic G12B SoC.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
 drivers/clk/meson/g12a.c | 66 ++++++++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/meson/g12a.h |  1 +
 2 files changed, 67 insertions(+)

diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index f373a8d48b1d..a8312f29d1cc 100644
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c
@@ -3722,6 +3722,66 @@ static struct clk_regmap g12a_mipi_dsi_pxclk = {
 	},
 };
 
+/* MIPI ISP Clocks */
+
+static const struct clk_parent_data g12b_mipi_isp_parent_data[] = {
+	{ .fw_name = "xtal", },
+	{ .hw = &g12a_gp0_pll.hw },
+	{ .hw = &g12a_hifi_pll.hw },
+	{ .hw = &g12a_fclk_div2p5.hw },
+	{ .hw = &g12a_fclk_div3.hw },
+	{ .hw = &g12a_fclk_div4.hw },
+	{ .hw = &g12a_fclk_div5.hw },
+	{ .hw = &g12a_fclk_div7.hw },
+};
+
+static struct clk_regmap g12b_mipi_isp_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = HHI_ISP_CLK_CNTL,
+		.mask = 7,
+		.shift = 9,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "mipi_isp_sel",
+		.ops = &clk_regmap_mux_ops,
+		.parent_data = g12b_mipi_isp_parent_data,
+		.num_parents = ARRAY_SIZE(g12b_mipi_isp_parent_data),
+	},
+};
+
+static struct clk_regmap g12b_mipi_isp_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = HHI_ISP_CLK_CNTL,
+		.shift = 0,
+		.width = 7,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "mipi_isp_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&g12b_mipi_isp_sel.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap g12b_mipi_isp = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = HHI_ISP_CLK_CNTL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "mipi_isp",
+		.ops = &clk_regmap_gate_ops,
+		.parent_hws = (const struct clk_hw *[]) {
+			&g12b_mipi_isp_div.hw
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
 /* HDMI Clocks */
 
 static const struct clk_parent_data g12a_hdmi_parent_data[] = {
@@ -4729,6 +4789,9 @@ static struct clk_hw *g12b_hw_clks[] = {
 	[CLKID_MIPI_DSI_PXCLK_SEL]	= &g12a_mipi_dsi_pxclk_sel.hw,
 	[CLKID_MIPI_DSI_PXCLK_DIV]	= &g12a_mipi_dsi_pxclk_div.hw,
 	[CLKID_MIPI_DSI_PXCLK]		= &g12a_mipi_dsi_pxclk.hw,
+	[CLKID_MIPI_ISP_SEL]		= &g12b_mipi_isp_sel.hw,
+	[CLKID_MIPI_ISP_DIV]		= &g12b_mipi_isp_div.hw,
+	[CLKID_MIPI_ISP]		= &g12b_mipi_isp.hw,
 };
 
 static struct clk_hw *sm1_hw_clks[] = {
@@ -5221,6 +5284,9 @@ static struct clk_regmap *const g12a_clk_regmaps[] = {
 	&g12a_mipi_dsi_pxclk_sel,
 	&g12a_mipi_dsi_pxclk_div,
 	&g12a_mipi_dsi_pxclk,
+	&g12b_mipi_isp_sel,
+	&g12b_mipi_isp_div,
+	&g12b_mipi_isp,
 };
 
 static const struct reg_sequence g12a_init_regs[] = {
diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h
index f11ee3c59849..27df99c4565a 100644
--- a/drivers/clk/meson/g12a.h
+++ b/drivers/clk/meson/g12a.h
@@ -70,6 +70,7 @@
 #define HHI_MALI_CLK_CNTL		0x1b0
 #define HHI_VPU_CLKC_CNTL		0x1b4
 #define HHI_VPU_CLK_CNTL		0x1bC
+#define HHI_ISP_CLK_CNTL		0x1C0
 #define HHI_NNA_CLK_CNTL		0x1C8
 #define HHI_HDMI_CLK_CNTL		0x1CC
 #define HHI_VDEC_CLK_CNTL		0x1E0

-- 
2.34.1

[PATCH 3/3] clk: meson: g12a: add CSI & ISP gates clocks

[Neil Armstrong]

Add the gates entires for the CSI ISP domain and CSI PHYs.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
 drivers/clk/meson/g12a.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index a8312f29d1cc..b0bd37ae1a81 100644
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c
@@ -4274,9 +4274,12 @@ static MESON_GATE(g12a_htx_hdcp22,		HHI_GCLK_MPEG2,	3);
 static MESON_GATE(g12a_htx_pclk,		HHI_GCLK_MPEG2,	4);
 static MESON_GATE(g12a_bt656,			HHI_GCLK_MPEG2,	6);
 static MESON_GATE(g12a_usb1_to_ddr,		HHI_GCLK_MPEG2,	8);
+static MESON_GATE(g12b_mipi_isp_gate,		HHI_GCLK_MPEG2,	17);
 static MESON_GATE(g12a_mmc_pclk,		HHI_GCLK_MPEG2,	11);
 static MESON_GATE(g12a_uart2,			HHI_GCLK_MPEG2,	15);
 static MESON_GATE(g12a_vpu_intr,		HHI_GCLK_MPEG2,	25);
+static MESON_GATE(g12b_csi_phy1,		HHI_GCLK_MPEG2,	28);
+static MESON_GATE(g12b_csi_phy0,		HHI_GCLK_MPEG2,	29);
 static MESON_GATE(g12a_gic,			HHI_GCLK_MPEG2,	30);
 
 static MESON_GATE(g12a_vclk2_venci0,		HHI_GCLK_OTHER,	1);
@@ -4792,6 +4795,9 @@ static struct clk_hw *g12b_hw_clks[] = {
 	[CLKID_MIPI_ISP_SEL]		= &g12b_mipi_isp_sel.hw,
 	[CLKID_MIPI_ISP_DIV]		= &g12b_mipi_isp_div.hw,
 	[CLKID_MIPI_ISP]		= &g12b_mipi_isp.hw,
+	[CLKID_MIPI_ISP_GATE]		= &g12b_mipi_isp_gate.hw,
+	[CLKID_MIPI_ISP_CSI_PHY0]	= &g12b_csi_phy0.hw,
+	[CLKID_MIPI_ISP_CSI_PHY1]	= &g12b_csi_phy1.hw,
 };
 
 static struct clk_hw *sm1_hw_clks[] = {
@@ -5287,6 +5293,9 @@ static struct clk_regmap *const g12a_clk_regmaps[] = {
 	&g12b_mipi_isp_sel,
 	&g12b_mipi_isp_div,
 	&g12b_mipi_isp,
+	&g12b_mipi_isp_gate,
+	&g12b_csi_phy1,
+	&g12b_csi_phy0,
 };
 
 static const struct reg_sequence g12a_init_regs[] = {

-- 
2.34.1

Re: [PATCH 0/3] clk: meson: add MIPI ISP & CSI PHY clocks

[Dan Scally]

Hi Neil - thanks for sending these!

On 14/11/2023 10:14, Neil Armstrong wrote:
> Add MIPI ISP & CSI PHY clock bindings and entries for
> the Amlogic G12B SoC.
>
> Based on the CTS_ENCL clock bindings patch at [1]
>
> [1] https://lore.kernel.org/all/20231109-amlogic-v6-4-upstream-dsi-ccf-vim3-v8-1-81e4aeeda193@linaro.org/
>
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---


Reviewed-by: Daniel Scally <dan.scally@ideasonboard.com>

and

Tested-by: Daniel Scally <dan.scally@ideasonboard.com>

> Neil Armstrong (3):
>        dt-bindings: clock: g12a-clkc: add MIPI ISP & CSI PHY clock ids
>        clk: meson: g12a: add MIPI ISP clocks
>        clk: meson: g12a: add CSI & ISP gates clocks
>
>   drivers/clk/meson/g12a.c              | 75 +++++++++++++++++++++++++++++++++++
>   drivers/clk/meson/g12a.h              |  1 +
>   include/dt-bindings/clock/g12a-clkc.h |  6 +++
>   3 files changed, 82 insertions(+)
> ---
> base-commit: 71ea46af56818a97cb5ea5d6554a0f10ea624d6d
> change-id: 20231114-topic-amlogic-upstream-isp-clocks-aa2859a633f0
>
> Best regards,

Re: [PATCH 0/3] clk: meson: add MIPI ISP & CSI PHY clocks

[Jerome Brunet]

Applied to clk-meson (v6.8/drivers), thanks!

[1/3] dt-bindings: clock: g12a-clkc: add MIPI ISP & CSI PHY clock ids
      https://github.com/BayLibre/clk-meson/commit/439d3404addf
[2/3] clk: meson: g12a: add MIPI ISP clocks
      https://github.com/BayLibre/clk-meson/commit/773e4e987308
[3/3] clk: meson: g12a: add CSI & ISP gates clocks
      https://github.com/BayLibre/clk-meson/commit/5205628ab0bf

Best regards,
--
Jerome