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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id z18-20020a9d7a52000000b006ce25d48e55sm205730otm.67.2023.11.14.06.12.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Nov 2023 06:12:56 -0800 (PST) Received: (nullmailer pid 1682194 invoked by uid 1000); Tue, 14 Nov 2023 14:12:55 -0000 Date: Tue, 14 Nov 2023 08:12:55 -0600 From: Rob Herring To: Daniel Golle Cc: Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Michael Turquette , Stephen Boyd , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Sabrina Dubroca , Jianhui Zhao , Chen-Yu Tsai , "Garmin.Chang" , Johnson Wang , Sam Shih , Frank Wunderlich , Dan Carpenter , Edward-JW Yang , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, netdev@vger.kernel.org Subject: Re: [PATCH 2/4] dt-bindings: clock: mediatek: add clock controllers of MT7988 Message-ID: <20231114141255.GA1678477-robh@kernel.org> References: <42c9447ae32be8aaeca2047a5e97660fb67dd286.1699909748.git.daniel@makrotopia.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <42c9447ae32be8aaeca2047a5e97660fb67dd286.1699909748.git.daniel@makrotopia.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Nov 13, 2023 at 09:12:19PM +0000, Daniel Golle wrote: > Add various clock controllers found in the MT7988 SoC to existing > bindings (if applicable) and add files for the new ethwarp, mcusys > and xfi-pll clock controllers not previously present in any previous > MediaTek SoC. > > Signed-off-by: Daniel Golle > --- > .../bindings/arm/mediatek/mediatek,ethsys.txt | 1 + > .../arm/mediatek/mediatek,infracfg.yaml | 1 + > .../arm/mediatek/mediatek,mt7988-ethwarp.yaml | 60 +++++++++++++++++++ > .../arm/mediatek/mediatek,mt7988-mcusys.yaml | 46 ++++++++++++++ > .../arm/mediatek/mediatek,mt7988-xfi-pll.yaml | 49 +++++++++++++++ > .../bindings/clock/mediatek,apmixedsys.yaml | 1 + > .../bindings/clock/mediatek,topckgen.yaml | 1 + > .../bindings/net/pcs/mediatek,sgmiisys.yaml | 2 + > 8 files changed, 161 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7988-ethwarp.yaml > create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7988-mcusys.yaml > create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7988-xfi-pll.yaml > > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt > index eccd4b706a78d..ac52579e03618 100644 > --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt > @@ -12,6 +12,7 @@ Required Properties: > - "mediatek,mt7629-ethsys", "syscon" > - "mediatek,mt7981-ethsys", "syscon" > - "mediatek,mt7986-ethsys", "syscon" > + - "mediatek,mt7988-ethsys", "syscon" > - #clock-cells: Must be 1 > - #reset-cells: Must be 1 > > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml > index ea98043c6ba3d..230b5188a88db 100644 > --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml > @@ -30,6 +30,7 @@ properties: > - mediatek,mt7629-infracfg > - mediatek,mt7981-infracfg > - mediatek,mt7986-infracfg > + - mediatek,mt7988-infracfg > - mediatek,mt8135-infracfg > - mediatek,mt8167-infracfg > - mediatek,mt8173-infracfg > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7988-ethwarp.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7988-ethwarp.yaml > new file mode 100644 > index 0000000000000..0c3d5e88b09df > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7988-ethwarp.yaml > @@ -0,0 +1,60 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7988-ethwarp.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek MT7988 ethwarp Controller > + > +maintainers: > + - Daniel Golle > + > +description: > + The Mediatek MT7988 ethwarp controller provides clocks and resets for the > + Ethernet related subsystems found the MT7988 SoC. > + The reset-controller can be represented using the ti,syscon-reset bindings. > + The clock values can be found in . > + > +properties: > + compatible: > + items: > + - const: mediatek,mt7988-ethwarp > + - const: syscon > + - const: simple-mfd > + > + reg: > + maxItems: 1 > + > + reset-controller: true type: object > + > + '#clock-cells': > + const: 1 > + > +required: > + - compatible > + - reg > + - '#clock-cells' > + > +additionalProperties: false > + > +examples: > + - | > + #include > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + ethwarp: clock-controller@15031000 { Drop unused labels. Elsewhere too. > + compatible = "mediatek,mt7988-ethwarp", "syscon", "simple-mfd"; > + reg = <0 0x15031000 0 0x1000>; > + #clock-cells = <1>; > + > + ethrst: reset-controller { > + compatible = "ti,syscon-reset"; > + #reset-cells = <1>; > + ti,reset-bits = < > + 0x8 9 0x8 9 0 0 (ASSERT_SET | DEASSERT_CLEAR | STATUS_NONE) > + >; > + }; > + }; > + };