From: "David E. Box" <david.e.box@linux.intel.com>
To: linux-kernel@vger.kernel.org,
platform-driver-x86@vger.kernel.org,
ilpo.jarvinen@linux.intel.com, rajvi.jingar@linux.intel.com
Subject: [PATCH V5 19/20] platform/x86/intel/pmc: Add debug attribute for Die C6 counter
Date: Wed, 22 Nov 2023 20:03:54 -0800 [thread overview]
Message-ID: <20231123040355.82139-20-david.e.box@linux.intel.com> (raw)
In-Reply-To: <20231123040355.82139-1-david.e.box@linux.intel.com>
Add a "die_c6_us_show" debugfs attribute. Reads the counter value using
Intel Platform Monitoring Technology (PMT) driver API. This counter is
useful for determining the idle residency of CPUs in the compute tile.
Also adds a missing forward declaration for punit_ep which was declared in
an earlier upstream commit but only used for the first time in this one.
Signed-off-by: David E. Box <david.e.box@linux.intel.com>
---
V5 - Change comment for crystal error and return value
V4 - no change
V3 - Split previous PATCH V2 13. Separates implementation (this patch) from
platform specific use (next patch)
V2 - Remove use of __func__
- Use HZ_PER_MHZ
- Fix missing newlines in printks
drivers/platform/x86/intel/pmc/core.c | 55 +++++++++++++++++++++++++++
drivers/platform/x86/intel/pmc/core.h | 4 ++
2 files changed, 59 insertions(+)
diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/intel/pmc/core.c
index 4a38d52558fd..fb2c84fba0ae 100644
--- a/drivers/platform/x86/intel/pmc/core.c
+++ b/drivers/platform/x86/intel/pmc/core.c
@@ -20,6 +20,7 @@
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/suspend.h>
+#include <linux/units.h>
#include <asm/cpu_device_id.h>
#include <asm/intel-family.h>
@@ -27,6 +28,7 @@
#include <asm/tsc.h>
#include "core.h"
+#include "../pmt/telemetry.h"
/* Maximum number of modes supported by platfoms that has low power mode capability */
const char *pmc_lpm_modes[] = {
@@ -817,6 +819,47 @@ static int pmc_core_substate_req_regs_show(struct seq_file *s, void *unused)
}
DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_req_regs);
+static unsigned int pmc_core_get_crystal_freq(void)
+{
+ unsigned int eax_denominator, ebx_numerator, ecx_hz, edx;
+
+ if (boot_cpu_data.cpuid_level < 0x15)
+ return 0;
+
+ eax_denominator = ebx_numerator = ecx_hz = edx = 0;
+
+ /* CPUID 15H TSC/Crystal ratio, plus optionally Crystal Hz */
+ cpuid(0x15, &eax_denominator, &ebx_numerator, &ecx_hz, &edx);
+
+ if (ebx_numerator == 0 || eax_denominator == 0)
+ return 0;
+
+ return ecx_hz;
+}
+
+static int pmc_core_die_c6_us_show(struct seq_file *s, void *unused)
+{
+ struct pmc_dev *pmcdev = s->private;
+ u64 die_c6_res, count;
+ int ret;
+
+ if (!pmcdev->crystal_freq) {
+ dev_warn_once(&pmcdev->pdev->dev, "Crystal frequency unavailable\n");
+ return -ENXIO;
+ }
+
+ ret = pmt_telem_read(pmcdev->punit_ep, pmcdev->die_c6_offset,
+ &count, 1);
+ if (ret)
+ return ret;
+
+ die_c6_res = div64_u64(count * HZ_PER_MHZ, pmcdev->crystal_freq);
+ seq_printf(s, "%llu\n", die_c6_res);
+
+ return 0;
+}
+DEFINE_SHOW_ATTRIBUTE(pmc_core_die_c6_us);
+
static int pmc_core_lpm_latch_mode_show(struct seq_file *s, void *unused)
{
struct pmc_dev *pmcdev = s->private;
@@ -1113,6 +1156,12 @@ static void pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
pmcdev->dbgfs_dir, pmcdev,
&pmc_core_substate_req_regs_fops);
}
+
+ if (pmcdev->has_die_c6) {
+ debugfs_create_file("die_c6_us_show", 0444,
+ pmcdev->dbgfs_dir, pmcdev,
+ &pmc_core_die_c6_us_fops);
+ }
}
static const struct x86_cpu_id intel_pmc_core_ids[] = {
@@ -1207,6 +1256,10 @@ static void pmc_core_clean_structure(struct platform_device *pdev)
pci_dev_put(pmcdev->ssram_pcidev);
pci_disable_device(pmcdev->ssram_pcidev);
}
+
+ if (pmcdev->punit_ep)
+ pmt_telem_unregister_endpoint(pmcdev->punit_ep);
+
platform_set_drvdata(pdev, NULL);
mutex_destroy(&pmcdev->lock);
}
@@ -1227,6 +1280,8 @@ static int pmc_core_probe(struct platform_device *pdev)
if (!pmcdev)
return -ENOMEM;
+ pmcdev->crystal_freq = pmc_core_get_crystal_freq();
+
platform_set_drvdata(pdev, pmcdev);
pmcdev->pdev = pdev;
diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/intel/pmc/core.h
index 85b6f6ae4995..6d7673145f90 100644
--- a/drivers/platform/x86/intel/pmc/core.h
+++ b/drivers/platform/x86/intel/pmc/core.h
@@ -16,6 +16,8 @@
#include <linux/bits.h>
#include <linux/platform_device.h>
+struct telem_endpoint;
+
#define SLP_S0_RES_COUNTER_MASK GENMASK(31, 0)
#define PMC_BASE_ADDR_DEFAULT 0xFE000000
@@ -357,6 +359,7 @@ struct pmc {
* @devs: pointer to an array of pmc pointers
* @pdev: pointer to platform_device struct
* @ssram_pcidev: pointer to pci device struct for the PMC SSRAM
+ * @crystal_freq: crystal frequency from cpuid
* @dbgfs_dir: path to debugfs interface
* @pmc_xram_read_bit: flag to indicate whether PMC XRAM shadow registers
* used to read MPHY PG and PLL status are available
@@ -374,6 +377,7 @@ struct pmc_dev {
struct dentry *dbgfs_dir;
struct platform_device *pdev;
struct pci_dev *ssram_pcidev;
+ unsigned int crystal_freq;
int pmc_xram_read_bit;
struct mutex lock; /* generic mutex lock for PMC Core */
--
2.34.1
next prev parent reply other threads:[~2023-11-23 4:05 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-23 4:03 [PATCH V5 00/20] intel_pmc: Add telemetry API to read counters David E. Box
2023-11-23 4:03 ` [PATCH V5 01/20] platform/x86/intel/vsec: Fix xa_alloc memory leak David E. Box
2023-11-23 11:27 ` Ilpo Järvinen
2023-11-23 15:27 ` Ilpo Järvinen
2023-11-23 4:03 ` [PATCH V5 02/20] platform/x86/intel/vsec: Move structures to header David E. Box
2023-11-23 4:03 ` [PATCH V5 03/20] platform/x86/intel/vsec: remove platform_info from vsec device structure David E. Box
2023-11-23 4:03 ` [PATCH V5 04/20] platform/x86/intel/vsec: Use cleanup.h David E. Box
2023-11-23 4:03 ` [PATCH V5 05/20] platform/x86/intel/vsec: Assign auxdev parent by argument David E. Box
2023-11-23 11:29 ` Ilpo Järvinen
2023-11-23 4:03 ` [PATCH V5 06/20] platform/x86/intel/vsec: Add intel_vsec_register David E. Box
2023-11-23 15:24 ` Ilpo Järvinen
2023-11-23 4:03 ` [PATCH V5 07/20] platform/x86/intel/vsec: Add base address field David E. Box
2023-11-23 4:03 ` [PATCH V5 08/20] platform/x86/intel/pmt: Add header to struct intel_pmt_entry David E. Box
2023-11-23 4:03 ` [PATCH V5 09/20] platform/x86/intel/pmt: telemetry: Export API to read telemetry David E. Box
2023-11-23 4:03 ` [PATCH V5 10/20] platform/x86:intel/pmc: Call pmc_get_low_power_modes from platform init David E. Box
2023-11-23 4:03 ` [PATCH V5 11/20] platform/x86/intel/pmc: Allow pmc_core_ssram_init to fail David E. Box
2023-11-23 4:03 ` [PATCH V5 12/20] asm-generic/io.h: iounmap/ioport_unmap cleanup.h support David E. Box
2023-11-23 14:30 ` Ilpo Järvinen
2023-11-23 16:23 ` David E. Box
2023-11-28 1:55 ` David E. Box
2023-11-29 8:45 ` Baoquan He
2023-12-10 15:24 ` Baoquan He
2023-11-24 9:49 ` kernel test robot
2023-11-23 4:03 ` [PATCH V5 13/20] platform/x86/intel/pmc: Cleanup SSRAM discovery David E. Box
2023-11-23 14:26 ` Ilpo Järvinen
2023-11-23 4:03 ` [PATCH V5 14/20] platform/x86/intel/pmc/mtl: Use return value from pmc_core_ssram_init() David E. Box
2023-11-23 14:26 ` Ilpo Järvinen
2023-11-23 4:03 ` [PATCH V5 15/20] platform/x86/intel/pmc: Find and register PMC telemetry entries David E. Box
2023-11-23 4:03 ` [PATCH V5 16/20] platform/x86/intel/pmc: Display LPM requirements for multiple PMCs David E. Box
2023-11-23 14:08 ` Ilpo Järvinen
2023-11-23 4:03 ` [PATCH V5 17/20] platform/x86/intel/pmc: Retrieve LPM information using Intel PMT David E. Box
2023-11-23 4:03 ` [PATCH V5 18/20] platform/x86/intel/pmc: Read low power mode requirements for MTL-M and MTL-P David E. Box
2023-11-23 4:03 ` David E. Box [this message]
2023-11-23 11:38 ` [PATCH V5 19/20] platform/x86/intel/pmc: Add debug attribute for Die C6 counter Ilpo Järvinen
2023-11-23 13:39 ` Ilpo Järvinen
2023-11-23 4:03 ` [PATCH V5 20/20] platform/x86/intel/pmc: Show Die C6 counter on Meteor Lake David E. Box
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