From: Eric Biggers <ebiggers@kernel.org>
To: Jerry Shih <jerry.shih@sifive.com>
Cc: paul.walmsley@sifive.com, palmer@dabbelt.com,
aou@eecs.berkeley.edu, herbert@gondor.apana.org.au,
davem@davemloft.net, conor.dooley@microchip.com, ardb@kernel.org,
heiko@sntech.de, phoebe.chen@sifive.com, hongrong.hsu@sifive.com,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-crypto@vger.kernel.org
Subject: Re: [PATCH v2 01/13] RISC-V: add helper function to read the vector VLEN
Date: Mon, 27 Nov 2023 19:45:17 -0800 [thread overview]
Message-ID: <20231128034517.GE1463@sol.localdomain> (raw)
In-Reply-To: <20231127070703.1697-2-jerry.shih@sifive.com>
On Mon, Nov 27, 2023 at 03:06:51PM +0800, Jerry Shih wrote:
> From: Heiko Stuebner <heiko.stuebner@vrull.eu>
>
> VLEN describes the length of each vector register and some instructions
> need specific minimal VLENs to work correctly.
>
> The vector code already includes a variable riscv_v_vsize that contains
> the value of "32 vector registers with vlenb length" that gets filled
> during boot. vlenb is the value contained in the CSR_VLENB register and
> the value represents "VLEN / 8".
>
> So add riscv_vector_vlen() to return the actual VLEN value for in-kernel
> users when they need to check the available VLEN.
>
> Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
> Signed-off-by: Jerry Shih <jerry.shih@sifive.com>
> ---
> arch/riscv/include/asm/vector.h | 11 +++++++++++
> 1 file changed, 11 insertions(+)
Reviewed-by: Eric Biggers <ebiggers@google.com>
- Eric
next prev parent reply other threads:[~2023-11-28 3:46 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-27 7:06 [PATCH v2 00/13] RISC-V: provide some accelerated cryptography implementations using vector extensions Jerry Shih
2023-11-27 7:06 ` [PATCH v2 01/13] RISC-V: add helper function to read the vector VLEN Jerry Shih
2023-11-28 3:45 ` Eric Biggers [this message]
2023-11-27 7:06 ` [PATCH v2 02/13] RISC-V: hook new crypto subdir into build-system Jerry Shih
2023-11-28 3:45 ` Eric Biggers
2023-11-27 7:06 ` [PATCH v2 03/13] RISC-V: crypto: add OpenSSL perl module for vector instructions Jerry Shih
2023-11-27 7:06 ` [PATCH v2 04/13] RISC-V: crypto: add Zvkned accelerated AES implementation Jerry Shih
2023-11-28 3:56 ` Eric Biggers
2023-11-28 4:22 ` Jerry Shih
2023-11-28 4:38 ` Eric Biggers
2023-11-28 17:54 ` Conor Dooley
2023-11-28 20:12 ` Eric Biggers
2023-11-29 2:39 ` Jerry Shih
2023-11-29 11:12 ` Conor Dooley
2023-11-29 20:26 ` Eric Biggers
2023-11-27 7:06 ` [PATCH v2 05/13] crypto: simd - Update `walksize` in simd skcipher Jerry Shih
2023-11-28 3:58 ` Eric Biggers
2023-11-28 5:38 ` Jerry Shih
2023-11-28 17:22 ` Eric Biggers
2023-12-01 2:09 ` Jerry Shih
2023-12-08 4:05 ` Herbert Xu
2023-12-08 4:18 ` Jerry Shih
2023-11-27 7:06 ` [PATCH v2 06/13] crypto: scatterwalk - Add scatterwalk_next() to get the next scatterlist in scatter_walk Jerry Shih
2023-11-27 7:06 ` [PATCH v2 07/13] RISC-V: crypto: add accelerated AES-CBC/CTR/ECB/XTS implementations Jerry Shih
2023-11-28 4:07 ` Eric Biggers
2023-11-29 7:57 ` Jerry Shih
2023-11-29 20:16 ` Eric Biggers
2023-12-02 13:20 ` Jerry Shih
2023-11-27 7:06 ` [PATCH v2 08/13] RISC-V: crypto: add Zvkg accelerated GCM GHASH implementation Jerry Shih
2023-11-27 7:06 ` [PATCH v2 09/13] RISC-V: crypto: add Zvknha/b accelerated SHA224/256 implementations Jerry Shih
2023-11-28 4:12 ` Eric Biggers
2023-11-28 7:16 ` Jerry Shih
2023-11-28 17:23 ` Eric Biggers
2023-11-27 7:07 ` [PATCH v2 10/13] RISC-V: crypto: add Zvknhb accelerated SHA384/512 implementations Jerry Shih
2023-11-27 7:07 ` [PATCH v2 11/13] RISC-V: crypto: add Zvksed accelerated SM4 implementation Jerry Shih
2023-11-27 7:07 ` [PATCH v2 12/13] RISC-V: crypto: add Zvksh accelerated SM3 implementation Jerry Shih
2023-11-28 4:13 ` Eric Biggers
2023-11-29 5:32 ` Jerry Shih
2023-11-27 7:07 ` [PATCH v2 13/13] RISC-V: crypto: add Zvkb accelerated ChaCha20 implementation Jerry Shih
2023-11-28 4:25 ` Eric Biggers
2023-11-28 8:57 ` Jerry Shih
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