From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9E11C4167B for ; Wed, 29 Nov 2023 23:21:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343638AbjK2XVG (ORCPT ); Wed, 29 Nov 2023 18:21:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45172 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229611AbjK2XVD (ORCPT ); Wed, 29 Nov 2023 18:21:03 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5A606A2 for ; Wed, 29 Nov 2023 15:21:10 -0800 (PST) Received: by smtp.kernel.org (Postfix) with ESMTPSA id CC51FC433C7; Wed, 29 Nov 2023 23:21:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1701300070; bh=9rdUMQCjtMr+ri5NEp2KYKHprcR+lytmbQP/lABcO2o=; h=Date:From:To:Cc:Subject:In-Reply-To:From; b=mkrHl0ULby81el9Tdi5wmgCfn8mVc0JBY/qTBKFuTKOV/yj+7U6oroEKfKUzCOved 68JatSVY8amXrxWOwXp8yrL7A+igA0ZVNVPNlQnoxAdWFAzfJYZZ/yRKafewoP1fwh Y7xdcggF8W5NWZFsbkbhnxj+t4zN/BLubFTqUQoPyZRD95PTbdjRkRv0QMKNisyNua NxZDw+rSP2x2atemkcLccbIEpl7JvhS7iyNJn7QmPR7nwxpiRQStzFpyjPPIF/f0O2 enVW6eVuZbJzypOGsxMn9opRGLvyLVUg2eZn6tmaEZBqZWekXrFB81eKVM2OCdeN5R KwJHqnTYXk8Hg== Date: Wed, 29 Nov 2023 17:21:08 -0600 From: Bjorn Helgaas To: Kevin Xie Cc: Bjorn Helgaas , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, mason.huo@starfivetech.com, leyfoon.tan@starfivetech.com, minda.chen@starfivetech.com Subject: Re: [PATCH v1] PCI: Add PCIE_CONFIG_REQUEST_WAIT_MS waiting time value Message-ID: <20231129232108.GA444155@bhelgaas> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20231124014508.43358-1-kevin.xie@starfivetech.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Nov 24, 2023 at 09:45:08AM +0800, Kevin Xie wrote: > Add the PCIE_CONFIG_REQUEST_WAIT_MS marco to define the minimum waiting > time between sending the first configuration request to the device and > exit from a conventional reset (or after link training completes). s/marco/macro/ List the first event before the second one, i.e., the delay is from exit from reset to the config request. > As described in the conventional reset rules of PCI specifications, > there are two different use cases of the value: > > - With a downstream port that supports link speeds <= 5.0 GT/s, > the waiting is following exit from a conventional reset. > > - With a downstream port that supports link speeds > 5.0 GT/s, > the waiting is after link training completes. Include the spec citation here as well as in the comment below. I assume there are follow-on patches that actually use this? Can we make this the first patch in a series so we know we don't have an unused macro lying around? > Signed-off-by: Kevin Xie > Reviewed-by: Mason Huo > --- > drivers/pci/pci.h | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h > index 5ecbcf041179..4ca8766e546e 100644 > --- a/drivers/pci/pci.h > +++ b/drivers/pci/pci.h > @@ -22,6 +22,13 @@ > */ > #define PCIE_PME_TO_L2_TIMEOUT_US 10000 > > +/* > + * PCIe r6.0, sec 6.6.1, > + * Requires a minimum waiting of 100ms before sending a configuration > + * request to the device. > + */ > +#define PCIE_CONFIG_REQUEST_WAIT_MS 100 > + > extern const unsigned char pcie_link_speed[]; > extern bool pci_early_dump; > > -- > 2.25.1 >