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Thu, 30 Nov 2023 18:15:29 +0000 Date: Fri, 1 Dec 2023 02:14:44 +0800 From: kernel test robot To: Benjamin Gaignard Cc: oe-kbuild-all@lists.linux.dev, linux-kernel@vger.kernel.org, Daniel Vetter Subject: drivers/gpu/drm/tilcdc/tilcdc_regs.h:141:39: sparse: sparse: incorrect type in assignment (different base types) Message-ID: <202312010230.nBVReHCy-lkp@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master head: 3b47bc037bd44f142ac09848e8d3ecccc726be99 commit: 62a0d98a188cc4ebd8ea54b37d274ec20465e464 drm: allow to use mmuless SoC date: 7 years ago config: arm-randconfig-r123-20231107 (https://download.01.org/0day-ci/archive/20231201/202312010230.nBVReHCy-lkp@intel.com/config) compiler: arm-linux-gnueabi-gcc (GCC) 13.2.0 reproduce: (https://download.01.org/0day-ci/archive/20231201/202312010230.nBVReHCy-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot | Closes: https://lore.kernel.org/oe-kbuild-all/202312010230.nBVReHCy-lkp@intel.com/ sparse warnings: (new ones prefixed by >>) drivers/gpu/drm/tilcdc/tilcdc_crtc.c: note: in included file: >> drivers/gpu/drm/tilcdc/tilcdc_regs.h:141:39: sparse: sparse: incorrect type in assignment (different base types) @@ expected unsigned long long volatile [usertype] @@ got restricted __le64 [usertype] @@ drivers/gpu/drm/tilcdc/tilcdc_regs.h:141:39: sparse: expected unsigned long long volatile [usertype] drivers/gpu/drm/tilcdc/tilcdc_regs.h:141:39: sparse: got restricted __le64 [usertype] vim +141 drivers/gpu/drm/tilcdc/tilcdc_regs.h 16ea975eac671fa Rob Clark 2013-01-08 130 7eb9f069ff5dd39 Jyri Sarha 2016-08-26 131 static inline void tilcdc_write64(struct drm_device *dev, u32 reg, u64 data) 7eb9f069ff5dd39 Jyri Sarha 2016-08-26 132 { 7eb9f069ff5dd39 Jyri Sarha 2016-08-26 133 struct tilcdc_drm_private *priv = dev->dev_private; 7eb9f069ff5dd39 Jyri Sarha 2016-08-26 134 volatile void __iomem *addr = priv->mmio + reg; 7eb9f069ff5dd39 Jyri Sarha 2016-08-26 135 7eb9f069ff5dd39 Jyri Sarha 2016-08-26 136 #ifdef iowrite64 7eb9f069ff5dd39 Jyri Sarha 2016-08-26 137 iowrite64(data, addr); 7eb9f069ff5dd39 Jyri Sarha 2016-08-26 138 #else 7eb9f069ff5dd39 Jyri Sarha 2016-08-26 139 __iowmb(); 7eb9f069ff5dd39 Jyri Sarha 2016-08-26 140 /* This compiles to strd (=64-bit write) on ARM7 */ 7eb9f069ff5dd39 Jyri Sarha 2016-08-26 @141 *(volatile u64 __force *)addr = __cpu_to_le64(data); 7eb9f069ff5dd39 Jyri Sarha 2016-08-26 142 #endif 7eb9f069ff5dd39 Jyri Sarha 2016-08-26 143 } 7eb9f069ff5dd39 Jyri Sarha 2016-08-26 144 :::::: The code at line 141 was first introduced by commit :::::: 7eb9f069ff5dd39d44d7ecdf63eb99b429c7dad0 drm/tilcdc: Write DMA base and ceiling address with single instruction :::::: TO: Jyri Sarha :::::: CC: Jyri Sarha -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki