From: Atish Patra <atishp@rivosinc.com>
To: linux-kernel@vger.kernel.org
Cc: Atish Patra <atishp@rivosinc.com>,
Alexandre Ghiti <alexghiti@rivosinc.com>,
Andrew Jones <ajones@ventanamicro.com>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
Conor Dooley <conor.dooley@microchip.com>,
Guo Ren <guoren@kernel.org>, Icenowy Zheng <uwu@icenowy.me>,
kvm-riscv@lists.infradead.org, kvm@vger.kernel.org,
linux-riscv@lists.infradead.org,
Mark Rutland <mark.rutland@arm.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Will Deacon <will@kernel.org>
Subject: [RFC 1/9] RISC-V: Fix the typo in Scountovf CSR name
Date: Mon, 4 Dec 2023 18:43:02 -0800 [thread overview]
Message-ID: <20231205024310.1593100-2-atishp@rivosinc.com> (raw)
In-Reply-To: <20231205024310.1593100-1-atishp@rivosinc.com>
The counter overflow CSR name is "scountovf" not "sscountovf".
Fix the csr name.
Fixes: 4905ec2fb7e6 ("RISC-V: Add sscofpmf extension support")
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
arch/riscv/include/asm/csr.h | 2 +-
arch/riscv/include/asm/errata_list.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 306a19a5509c..88cdc8a3e654 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -281,7 +281,7 @@
#define CSR_HPMCOUNTER30H 0xc9e
#define CSR_HPMCOUNTER31H 0xc9f
-#define CSR_SSCOUNTOVF 0xda0
+#define CSR_SCOUNTOVF 0xda0
#define CSR_SSTATUS 0x100
#define CSR_SIE 0x104
diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
index 83ed25e43553..7026fba12eeb 100644
--- a/arch/riscv/include/asm/errata_list.h
+++ b/arch/riscv/include/asm/errata_list.h
@@ -152,7 +152,7 @@ asm volatile(ALTERNATIVE_2( \
#define ALT_SBI_PMU_OVERFLOW(__ovl) \
asm volatile(ALTERNATIVE( \
- "csrr %0, " __stringify(CSR_SSCOUNTOVF), \
+ "csrr %0, " __stringify(CSR_SCOUNTOVF), \
"csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF), \
THEAD_VENDOR_ID, ERRATA_THEAD_PMU, \
CONFIG_ERRATA_THEAD_PMU) \
--
2.34.1
next prev parent reply other threads:[~2023-12-05 2:43 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-05 2:43 [RFC 0/9] RISC-V SBI v2.0 PMU improvements and Perf sampling in KVM guest Atish Patra
2023-12-05 2:43 ` Atish Patra [this message]
2023-12-07 12:04 ` [RFC 1/9] RISC-V: Fix the typo in Scountovf CSR name Conor Dooley
2023-12-14 12:13 ` Anup Patel
2023-12-05 2:43 ` [RFC 2/9] drivers/perf: riscv: Add a flag to indicate SBI v2.0 support Atish Patra
2023-12-07 12:07 ` Conor Dooley
2023-12-14 12:15 ` Anup Patel
2023-12-16 23:54 ` Atish Kumar Patra
2023-12-05 2:43 ` [RFC 3/9] RISC-V: Add FIRMWARE_READ_HI definition Atish Patra
2023-12-07 12:11 ` Conor Dooley
2023-12-14 12:16 ` Anup Patel
2023-12-05 2:43 ` [RFC 4/9] drivers/perf: riscv: Read upper bits of a firmware counter Atish Patra
2023-12-07 12:32 ` Conor Dooley
2023-12-14 12:30 ` Anup Patel
2023-12-16 23:54 ` Atish Kumar Patra
2023-12-05 2:43 ` [RFC 5/9] RISC-V: Add SBI PMU snapshot definitions Atish Patra
2023-12-07 12:33 ` Conor Dooley
2023-12-16 23:33 ` Atish Patra
2023-12-14 12:32 ` Anup Patel
2023-12-05 2:43 ` [RFC 6/9] drivers/perf: riscv: Implement SBI PMU snapshot function Atish Patra
2023-12-07 13:05 ` Conor Dooley
2023-12-17 1:39 ` Atish Kumar Patra
2023-12-17 12:10 ` Conor Dooley
2023-12-18 0:57 ` Atish Kumar Patra
2023-12-05 2:43 ` [RFC 7/9] RISC-V: KVM: Implement SBI PMU Snapshot feature Atish Patra
2023-12-14 13:46 ` Anup Patel
2023-12-17 9:36 ` Atish Kumar Patra
2023-12-05 2:43 ` [RFC 8/9] RISC-V: KVM: Add perf sampling support for guests Atish Patra
2023-12-06 6:43 ` Vladimir Isaev
2023-12-06 7:41 ` Atish Kumar Patra
2023-12-14 16:02 ` Anup Patel
2023-12-17 1:48 ` Atish Kumar Patra
2023-12-05 2:43 ` [RFC 9/9] RISC-V: KVM: Support 64 bit firmware counters on RV32 Atish Patra
2023-12-14 12:41 ` Anup Patel
2023-12-07 12:02 ` [RFC 0/9] RISC-V SBI v2.0 PMU improvements and Perf sampling in KVM guest Conor Dooley
2023-12-07 22:28 ` Atish Kumar Patra
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