From: Rex Zhang <rex.zhang@intel.com>
To: tom.zanussi@linux.intel.com
Cc: dave.jiang@intel.com, davem@davemloft.net,
dmaengine@vger.kernel.org, fenghua.yu@intel.com,
giovanni.cabiddu@intel.com, herbert@gondor.apana.org.au,
james.guilford@intel.com, kanchana.p.sridhar@intel.com,
linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org,
pavel@ucw.cz, tony.luck@intel.com, vinodh.gopal@intel.com,
vkoul@kernel.org, wajdi.k.feghali@intel.com
Subject: Re: [PATCH v11 14/14] dmaengine: idxd: Add support for device/wq defaults
Date: Tue, 5 Dec 2023 17:21:39 +0800 [thread overview]
Message-ID: <20231205092139.3682047-1-rex.zhang@intel.com> (raw)
In-Reply-To: <20231201201035.172465-15-tom.zanussi@linux.intel.com>
Hi Tom,
On 2023-12-01 at 14:10:35 -0600, Tom Zanussi wrote:
[snip]
> +int idxd_load_iaa_device_defaults(struct idxd_device *idxd)
> +{
> + struct idxd_engine *engine;
> + struct idxd_group *group;
> + struct idxd_wq *wq;
> +
> + if (!test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags))
> + return 0;
In the virtualization case, it is not configurable in guest OS,
then the default work queue will not be enabled. Is it expected?
> +
> + wq = idxd->wqs[0];
> +
> + if (wq->state != IDXD_WQ_DISABLED)
> + return -EPERM;
> +
> + /* set mode to "dedicated" */
> + set_bit(WQ_FLAG_DEDICATED, &wq->flags);
> + wq->threshold = 0;
> +
> + /* only setting up 1 wq, so give it all the wq space */
> + wq->size = idxd->max_wq_size;
> +
> + /* set priority to 10 */
> + wq->priority = 10;
> +
> + /* set type to "kernel" */
> + wq->type = IDXD_WQT_KERNEL;
> +
> + /* set wq group to 0 */
> + group = idxd->groups[0];
> + wq->group = group;
> + group->num_wqs++;
> +
> + /* set name to "iaa_crypto" */
> + memset(wq->name, 0, WQ_NAME_SIZE + 1);
> + strscpy(wq->name, "iaa_crypto", WQ_NAME_SIZE + 1);
> +
> + /* set driver_name to "crypto" */
> + memset(wq->driver_name, 0, DRIVER_NAME_SIZE + 1);
> + strscpy(wq->driver_name, "crypto", DRIVER_NAME_SIZE + 1);
> +
> + engine = idxd->engines[0];
> +
> + /* set engine group to 0 */
> + engine->group = idxd->groups[0];
> + engine->group->num_engines++;
> +
> + return 0;
> +}
> diff --git a/drivers/dma/idxd/idxd.h b/drivers/dma/idxd/idxd.h
> index 62ea21b25906..47de3f93ff1e 100644
> --- a/drivers/dma/idxd/idxd.h
> +++ b/drivers/dma/idxd/idxd.h
> @@ -277,6 +277,8 @@ struct idxd_dma_dev {
> struct dma_device dma;
> };
>
> +typedef int (*load_device_defaults_fn_t) (struct idxd_device *idxd);
> +
> struct idxd_driver_data {
> const char *name_prefix;
> enum idxd_type type;
> @@ -286,6 +288,7 @@ struct idxd_driver_data {
> int evl_cr_off;
> int cr_status_off;
> int cr_result_off;
> + load_device_defaults_fn_t load_device_defaults;
> };
>
> struct idxd_evl {
> @@ -730,6 +733,7 @@ void idxd_unregister_devices(struct idxd_device *idxd);
> void idxd_wqs_quiesce(struct idxd_device *idxd);
> bool idxd_queue_int_handle_resubmit(struct idxd_desc *desc);
> void multi_u64_to_bmap(unsigned long *bmap, u64 *val, int count);
> +int idxd_load_iaa_device_defaults(struct idxd_device *idxd);
>
> /* device interrupt control */
> irqreturn_t idxd_misc_thread(int vec, void *data);
> diff --git a/drivers/dma/idxd/init.c b/drivers/dma/idxd/init.c
> index 0eb1c827a215..14df1f1347a8 100644
> --- a/drivers/dma/idxd/init.c
> +++ b/drivers/dma/idxd/init.c
> @@ -59,6 +59,7 @@ static struct idxd_driver_data idxd_driver_data[] = {
> .evl_cr_off = offsetof(struct iax_evl_entry, cr),
> .cr_status_off = offsetof(struct iax_completion_record, status),
> .cr_result_off = offsetof(struct iax_completion_record, error_code),
> + .load_device_defaults = idxd_load_iaa_device_defaults,
> },
> };
>
> @@ -745,6 +746,12 @@ static int idxd_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
> goto err;
> }
>
> + if (data->load_device_defaults) {
> + rc = data->load_device_defaults(idxd);
> + if (rc)
> + dev_warn(dev, "IDXD loading device defaults failed\n");
> + }
> +
> rc = idxd_register_devices(idxd);
> if (rc) {
> dev_err(dev, "IDXD sysfs setup failed\n");
Thanks,
Rex Zhang
> --
> 2.34.1
>
next prev parent reply other threads:[~2023-12-05 9:21 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-01 20:10 [PATCH v11 00/14] crypto: Add Intel Analytics Accelerator (IAA) crypto compression driver Tom Zanussi
2023-12-01 20:10 ` [PATCH v11 01/14] dmaengine: idxd: add external module driver support for dsa_bus_type Tom Zanussi
2023-12-01 20:10 ` [PATCH v11 02/14] dmaengine: idxd: Rename drv_enable/disable_wq to idxd_drv_enable/disable_wq, and export Tom Zanussi
2023-12-01 20:10 ` [PATCH v11 03/14] dmaengine: idxd: Export descriptor management functions Tom Zanussi
2023-12-01 20:10 ` [PATCH v11 04/14] dmaengine: idxd: Export wq resource " Tom Zanussi
2023-12-01 20:10 ` [PATCH v11 05/14] dmaengine: idxd: Add wq private data accessors Tom Zanussi
2023-12-01 20:10 ` [PATCH v11 06/14] dmaengine: idxd: add callback support for iaa crypto Tom Zanussi
2023-12-01 20:10 ` [PATCH v11 07/14] crypto: iaa - Add IAA Compression Accelerator Documentation Tom Zanussi
2023-12-01 20:10 ` [PATCH v11 08/14] crypto: iaa - Add Intel IAA Compression Accelerator crypto driver core Tom Zanussi
2023-12-01 20:10 ` [PATCH v11 09/14] crypto: iaa - Add per-cpu workqueue table with rebalancing Tom Zanussi
2023-12-01 20:10 ` [PATCH v11 10/14] crypto: iaa - Add compression mode management along with fixed mode Tom Zanussi
2023-12-01 20:10 ` [PATCH v11 11/14] crypto: iaa - Add support for deflate-iaa compression algorithm Tom Zanussi
2023-12-04 15:00 ` Rex Zhang
2023-12-04 21:41 ` Tom Zanussi
2023-12-05 2:26 ` Rex Zhang
2023-12-05 21:18 ` Tom Zanussi
2023-12-01 20:10 ` [PATCH v11 12/14] crypto: iaa - Add irq support for the crypto async interface Tom Zanussi
2023-12-01 20:10 ` [PATCH v11 13/14] crypto: iaa - Add IAA Compression Accelerator stats Tom Zanussi
2023-12-01 20:10 ` [PATCH v11 14/14] dmaengine: idxd: Add support for device/wq defaults Tom Zanussi
2023-12-05 9:21 ` Rex Zhang [this message]
2023-12-05 15:52 ` Dave Jiang
2023-12-08 20:12 ` Fenghua Yu
2023-12-08 22:13 ` Tom Zanussi
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