drivers/edac/versal_edac.c:745:21: sparse: sparse: incorrect type in argument 1 (different address spaces)

[kernel test robot <lkp@intel.com>]

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head:   bee0e7762ad2c6025b9f5245c040fcc36ef2bde8
commit: 6f15b178cd6315c997981f76c6ebed7ad39144c5 EDAC/versal: Add a Xilinx Versal memory controller driver
date:   6 weeks ago
config: riscv-randconfig-r131-20231203 (https://download.01.org/0day-ci/archive/20231206/202312060244.Y1Aw12Kr-lkp@intel.com/config)
compiler: clang version 15.0.7 (https://github.com/llvm/llvm-project.git 8dfdcc7b7bf66834a761bd8de445840ef68e4d1a)
reproduce: (https://download.01.org/0day-ci/archive/20231206/202312060244.Y1Aw12Kr-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202312060244.Y1Aw12Kr-lkp@intel.com/

sparse warnings: (new ones prefixed by >>)
   WARNING: invalid argument to '-march': '_zihintpause'
>> drivers/edac/versal_edac.c:745:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@     expected char const *cs @@     got char const [noderef] __user *data @@
   drivers/edac/versal_edac.c:745:21: sparse:     expected char const *cs
   drivers/edac/versal_edac.c:745:21: sparse:     got char const [noderef] __user *data

vim +745 drivers/edac/versal_edac.c

   736	
   737	static ssize_t xddr_inject_data_poison_store(struct mem_ctl_info *mci,
   738						     const char __user *data)
   739	{
   740		struct edac_priv *priv = mci->pvt_info;
   741	
   742		writel(0, priv->ddrmc_baseaddr + ECCW0_FLIP0_OFFSET);
   743		writel(0, priv->ddrmc_baseaddr + ECCW1_FLIP0_OFFSET);
   744	
 > 745		if (strncmp(data, "CE", 2) == 0) {
   746			writel(ECC_CEPOISON_MASK, priv->ddrmc_baseaddr +
   747			       ECCW0_FLIP0_OFFSET);
   748			writel(ECC_CEPOISON_MASK, priv->ddrmc_baseaddr +
   749			       ECCW1_FLIP0_OFFSET);
   750		} else {
   751			writel(ECC_UEPOISON_MASK, priv->ddrmc_baseaddr +
   752			       ECCW0_FLIP0_OFFSET);
   753			writel(ECC_UEPOISON_MASK, priv->ddrmc_baseaddr +
   754			       ECCW1_FLIP0_OFFSET);
   755		}
   756	
   757		/* Lock the PCSR registers */
   758		writel(1, priv->ddrmc_baseaddr + XDDR_PCSR_OFFSET);
   759	
   760		return 0;
   761	}
   762	

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