Re: [PATCH v2 10/16] drm/msm/dpu: add CDM related logic to dpu_hw_ctl layer

[kernel test robot <lkp@intel.com>]

Hi Abhinav,

kernel test robot noticed the following build warnings:

[auto build test WARNING on next-20231207]
[also build test WARNING on v6.7-rc4]
[cannot apply to drm-misc/drm-misc-next linus/master v6.7-rc4 v6.7-rc3 v6.7-rc2]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Abhinav-Kumar/drm-msm-dpu-add-formats-check-for-writeback-encoder/20231208-130820
base:   next-20231207
patch link:    https://lore.kernel.org/r/20231208050641.32582-11-quic_abhinavk%40quicinc.com
patch subject: [PATCH v2 10/16] drm/msm/dpu: add CDM related logic to dpu_hw_ctl layer
config: x86_64-allyesconfig (https://download.01.org/0day-ci/archive/20231210/202312102047.S0I69pCs-lkp@intel.com/config)
compiler: clang version 16.0.4 (https://github.com/llvm/llvm-project.git ae42196bc493ffe877a7e3dff8be32035dea4d07)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231210/202312102047.S0I69pCs-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202312102047.S0I69pCs-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c:537:6: warning: variable 'cdm_active' set but not used [-Wunused-but-set-variable]
           u32 cdm_active = 0;
               ^
   1 warning generated.


vim +/cdm_active +537 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

   528	
   529	
   530	static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
   531			struct dpu_hw_intf_cfg *cfg)
   532	{
   533		struct dpu_hw_blk_reg_map *c = &ctx->hw;
   534		u32 intf_active = 0;
   535		u32 wb_active = 0;
   536		u32 mode_sel = 0;
 > 537		u32 cdm_active = 0;
   538	
   539		/* CTL_TOP[31:28] carries group_id to collate CTL paths
   540		 * per VM. Explicitly disable it until VM support is
   541		 * added in SW. Power on reset value is not disable.
   542		 */
   543		if ((test_bit(DPU_CTL_VM_CFG, &ctx->caps->features)))
   544			mode_sel = CTL_DEFAULT_GROUP_ID  << 28;
   545	
   546		if (cfg->intf_mode_sel == DPU_CTL_MODE_SEL_CMD)
   547			mode_sel |= BIT(17);
   548	
   549		intf_active = DPU_REG_READ(c, CTL_INTF_ACTIVE);
   550		wb_active = DPU_REG_READ(c, CTL_WB_ACTIVE);
   551		cdm_active = DPU_REG_READ(c, CTL_CDM_ACTIVE);
   552	
   553		if (cfg->intf)
   554			intf_active |= BIT(cfg->intf - INTF_0);
   555	
   556		if (cfg->wb)
   557			wb_active |= BIT(cfg->wb - WB_0);
   558	
   559		DPU_REG_WRITE(c, CTL_TOP, mode_sel);
   560		DPU_REG_WRITE(c, CTL_INTF_ACTIVE, intf_active);
   561		DPU_REG_WRITE(c, CTL_WB_ACTIVE, wb_active);
   562	
   563		if (cfg->merge_3d)
   564			DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE,
   565				      BIT(cfg->merge_3d - MERGE_3D_0));
   566	
   567		if (cfg->dsc)
   568			DPU_REG_WRITE(c, CTL_DSC_ACTIVE, cfg->dsc);
   569	
   570		if (cfg->cdm)
   571			DPU_REG_WRITE(c, CTL_CDM_ACTIVE, cfg->cdm);
   572	}
   573	

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