From: "Clément Léger" <cleger@rivosinc.com>
To: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Cc: "Clément Léger" <cleger@rivosinc.com>,
"Jonathan Corbet" <corbet@lwn.net>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Conor Dooley" <conor@kernel.org>,
"Rob Herring" <robh+dt@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Robbin Ehn" <rehn@rivosinc.com>
Subject: [PATCH 8/9] riscv: hwprobe: export Zacas ISA extension
Date: Wed, 13 Dec 2023 12:33:04 +0100 [thread overview]
Message-ID: <20231213113308.133176-9-cleger@rivosinc.com> (raw)
In-Reply-To: <20231213113308.133176-1-cleger@rivosinc.com>
Export Zacas ISA extension through hwprobe.
Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
Documentation/arch/riscv/hwprobe.rst | 4 ++++
arch/riscv/include/uapi/asm/hwprobe.h | 1 +
arch/riscv/kernel/sys_riscv.c | 1 +
3 files changed, 6 insertions(+)
diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index 9b19ca3433de..510e49878834 100644
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -168,6 +168,10 @@ The following keys are defined:
* :c:macro:`RISCV_HWPROBE_EXT_ZAM`: The Zam extension v0.1 is supported as
defined in the RISC-V ISA manual.
+ * :c:macro:`RISCV_HWPROBE_EXT_ZACAS`: The Zacas extension is supported as
+ defined in the Atomic Compare-and-Swap (CAS) instructions manual starting
+ from commit 5059e0ca641c ("update to ratified").
+
* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
information about the selected set of processors.
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index 2350c45741a6..7ec4331122e7 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -58,6 +58,7 @@ struct riscv_hwprobe {
#define RISCV_HWPROBE_EXT_ZFA (1ULL << 32)
#define RISCV_HWPROBE_EXT_ZTSO (1ULL << 33)
#define RISCV_HWPROBE_EXT_ZAM (1ULL << 34)
+#define RISCV_HWPROBE_EXT_ZACAS (1ULL << 35)
#define RISCV_HWPROBE_KEY_CPUPERF_0 5
#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c
index a8473d7f9d1e..abb0eea3ee08 100644
--- a/arch/riscv/kernel/sys_riscv.c
+++ b/arch/riscv/kernel/sys_riscv.c
@@ -176,6 +176,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
EXT_KEY(ZIHINTNTL);
EXT_KEY(ZTSO);
EXT_KEY(ZAM);
+ EXT_KEY(ZACAS);
if (has_vector()) {
EXT_KEY(ZVBB);
--
2.43.0
next prev parent reply other threads:[~2023-12-13 11:34 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-13 11:32 [PATCH 0/9] riscv: hwprobe: add Zicond, Zam, Zacas and Ztso support Clément Léger
2023-12-13 11:32 ` [PATCH 1/9] riscv: add ISA extension parsing for Ztso Clément Léger
2023-12-13 11:32 ` [PATCH 2/9] riscv: hwprobe: export Ztso ISA extension Clément Léger
2023-12-13 11:32 ` [PATCH 3/9] dt-bindings: riscv: add Zam ISA extension description Clément Léger
2023-12-14 14:11 ` Conor Dooley
2023-12-15 8:26 ` Clément Léger
2023-12-13 11:33 ` [PATCH 4/9] riscv: add ISA extension parsing for Zam Clément Léger
2023-12-14 14:14 ` Conor Dooley
2023-12-13 11:33 ` [PATCH 5/9] riscv: hwprobe: export Zam ISA extension Clément Léger
2023-12-13 11:33 ` [PATCH 6/9] dt-bindings: riscv: add Zacas ISA extension description Clément Léger
2023-12-14 14:12 ` Conor Dooley
2023-12-13 11:33 ` [PATCH 7/9] riscv: add ISA extension parsing for Zacas Clément Léger
2023-12-13 11:33 ` Clément Léger [this message]
2023-12-13 11:33 ` [PATCH 9/9] riscv: hwprobe: export Zicond extension Clément Léger
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