From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1E11840BE8; Tue, 19 Dec 2023 17:01:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="SuEqlBue" Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-40d31116dbeso617565e9.3; Tue, 19 Dec 2023 09:01:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1703005290; x=1703610090; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yPHQ4Axf1Zj8/9D5WH9YQvs+oHeh2coMc0soFZ2d7Pc=; b=SuEqlBueYYAPCOfrwNoyduvyb6y8VuQy8DnRXpKZhrMjqaw/slOw6kSClqFBM39NOo K5KRd7KRA7tyk9fMLpjLADObKyvS+F7ApE6krdcLbwMLOn20jNOIFJvm8Ho9/S9665Xb nVJ5f8LgJjZ8dDBdF1jq2oqyDYNhwnPLLaVZCjTK4veQlbUCeCbfCrxiLKla4NsKlG5k +a4auZdUCd6xEBREUQxw8meU2/0eZBM98w5jtg5w3c/l46Bq5TlhWBj9M7J4sFZ5jvBH iexU4THgkd173Z8PjAtPo9i7E8H9S5gphA7Jlwi2jfQRz4pxysaFnNO7jG5WsSsU8c5w blGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703005290; x=1703610090; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yPHQ4Axf1Zj8/9D5WH9YQvs+oHeh2coMc0soFZ2d7Pc=; b=l5gVJhQif+BFzqXtWxA7nEAiC74bCWimC7hcICVPoCjU1aCbTpHgJBHHdxQvxpEl4N RaHn+XylsM7xHt7O2tJCTS+C10kOXFVhWC+tQcTBjsOp98OjlPINgLvIi88b+1zsreya 30mMK4eWRILk4KuKsPovnhUOL3Pw6mrvmlUGCvcd3rInL2ACXXlV081P9wwJd9cvS6v4 s+LnTLLB6j/erq0wbj/H56nmgoJ0pywYmkNP3aSsl9kwTadhpuCVAM/rNI+bfQMPiLJS F82ol8ynGU3G6LrBa1gapJvHjpdhWM/LoyDtux6p4CYBzMR0CqQJseqROItZuGx0hW1L IHIA== X-Gm-Message-State: AOJu0YxvPTqwOks2BFOzZZTuF4TZKKsyyJFesHT5bsi7glEcBvBTriAW gYDlIZAhVkj+apQJzN8zLg== X-Google-Smtp-Source: AGHT+IE4eDamrkaqHIRmRipnXIk9NA5k22v04gAX2DztUoFzEGsVq5zIRkBu0fqdPB7W0SQaCaXYPA== X-Received: by 2002:a05:600c:538e:b0:40d:2055:8088 with SMTP id hg14-20020a05600c538e00b0040d20558088mr938934wmb.158.1703005290201; Tue, 19 Dec 2023 09:01:30 -0800 (PST) Received: from U4.lan ([2a02:810b:f40:4300:7ae5:3e:d1c6:a138]) by smtp.gmail.com with ESMTPSA id i7-20020a05600c354700b0040d2805d158sm3225878wmq.48.2023.12.19.09.01.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 09:01:28 -0800 (PST) From: Alex Bee To: Sandy Huang , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: David Airlie , Daniel Vetter , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Alex Bee Subject: [PATCH v3 24/29] drm/rockchip: inno_hdmi: Add RK3128 support Date: Tue, 19 Dec 2023 18:00:54 +0100 Message-ID: <20231219170100.188800-25-knaerzche@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231219170100.188800-1-knaerzche@gmail.com> References: <20231219170100.188800-1-knaerzche@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit This variant requires the phy reference clock to be enabled before the DDC block can work and the (initial) DDC bus frequency is calculated based on the rate of this clock. Besides the only difference is phy configuration required to make the driver working for this variant as well. Signed-off-by: Alex Bee --- changes in v2: - no changes changes in v3: - no changes drivers/gpu/drm/rockchip/inno_hdmi.c | 46 +++++++++++++++++++++++++--- 1 file changed, 41 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/rockchip/inno_hdmi.c b/drivers/gpu/drm/rockchip/inno_hdmi.c index df979bab9abd..8a1a2320749a 100644 --- a/drivers/gpu/drm/rockchip/inno_hdmi.c +++ b/drivers/gpu/drm/rockchip/inno_hdmi.c @@ -51,6 +51,7 @@ struct inno_hdmi { struct device *dev; struct clk *pclk; + struct clk *refclk; void __iomem *regs; struct drm_connector connector; @@ -132,6 +133,12 @@ static struct inno_hdmi_phy_config rk3036_hdmi_phy_configs[] = { { ~0UL, 0x00, 0x00 } }; +static struct inno_hdmi_phy_config rk3128_hdmi_phy_configs[] = { + { 74250000, 0x3f, 0xaa }, + { 165000000, 0x5f, 0xaa }, + { ~0UL, 0x00, 0x00 } +}; + static int inno_hdmi_find_phy_config(struct inno_hdmi *hdmi, unsigned long pixelclk) { @@ -905,6 +912,20 @@ static int inno_hdmi_bind(struct device *dev, struct device *master, return ret; } + hdmi->refclk = devm_clk_get_optional(hdmi->dev, "ref"); + if (IS_ERR(hdmi->refclk)) { + DRM_DEV_ERROR(hdmi->dev, "Unable to get HDMI reference clock\n"); + ret = PTR_ERR(hdmi->refclk); + goto err_disable_pclk; + } + + ret = clk_prepare_enable(hdmi->refclk); + if (ret) { + DRM_DEV_ERROR(hdmi->dev, + "Cannot enable HDMI reference clock: %d\n", ret); + goto err_disable_pclk; + } + irq = platform_get_irq(pdev, 0); if (irq < 0) { ret = irq; @@ -921,12 +942,16 @@ static int inno_hdmi_bind(struct device *dev, struct device *master, } /* - * When IP controller haven't configured to an accurate video - * timing, then the TMDS clock source would be switched to - * PCLK_HDMI, so we need to init the TMDS rate to PCLK rate, - * and reconfigure the DDC clock. + * When the controller isn't configured to an accurate + * video timing and there is no reference clock available, + * then the TMDS clock source would be switched to PCLK_HDMI, + * so we need to init the TMDS rate to PCLK rate, and + * reconfigure the DDC clock. */ - inno_hdmi_i2c_init(hdmi, clk_get_rate(hdmi->pclk)); + if (hdmi->refclk) + inno_hdmi_i2c_init(hdmi, clk_get_rate(hdmi->refclk)); + else + inno_hdmi_i2c_init(hdmi, clk_get_rate(hdmi->pclk)); ret = inno_hdmi_register(drm, hdmi); if (ret) @@ -950,6 +975,8 @@ static int inno_hdmi_bind(struct device *dev, struct device *master, err_put_adapter: i2c_put_adapter(hdmi->ddc); err_disable_clk: + clk_disable_unprepare(hdmi->refclk); +err_disable_pclk: clk_disable_unprepare(hdmi->pclk); return ret; } @@ -963,6 +990,7 @@ static void inno_hdmi_unbind(struct device *dev, struct device *master, hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder); i2c_put_adapter(hdmi->ddc); + clk_disable_unprepare(hdmi->refclk); clk_disable_unprepare(hdmi->pclk); } @@ -986,10 +1014,18 @@ static const struct inno_hdmi_variant rk3036_inno_hdmi_variant = { .default_phy_config = &rk3036_hdmi_phy_configs[1], }; +static const struct inno_hdmi_variant rk3128_inno_hdmi_variant = { + .phy_configs = rk3128_hdmi_phy_configs, + .default_phy_config = &rk3128_hdmi_phy_configs[1], +}; + static const struct of_device_id inno_hdmi_dt_ids[] = { { .compatible = "rockchip,rk3036-inno-hdmi", .data = &rk3036_inno_hdmi_variant, }, + { .compatible = "rockchip,rk3128-inno-hdmi", + .data = &rk3128_inno_hdmi_variant, + }, {}, }; MODULE_DEVICE_TABLE(of, inno_hdmi_dt_ids); -- 2.43.0