From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E6C235282; Tue, 19 Dec 2023 17:01:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Co3vCXU7" Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-40c3fe6c1b5so52521435e9.2; Tue, 19 Dec 2023 09:01:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1703005269; x=1703610069; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tvxDLNOYjKdWlkXmI7fVu1cGUQmdpgYMh9GlbetV5JM=; b=Co3vCXU7dJYa1o7tTkeZLSAlruhBwV0IYqLPnN9vesnMrvLbO/EjzMkEjR/JgaUpyy BFyHy+gHl6YyJEsKjHtnXiCIwwylNXygeYYPj5Z8/mRlZ7ob9EYxP0ykRZdWE/gx/Xgs TEc8zYvzVihsF/tglIFfK79slhw5O28p3fPBRPJRWy9IjhVS6Xi+/uHH+ivTM/Fu2dWs g7K8Nevf2YrXoiOI5oKndxrtGLyWcLlAo52pgjBs5qcuBE1jx53IhPqBQz699OKmz1Rk 4dypbTbXdKjrrbHDvYhaZED6PX/iBFatbTNOHWL4YCYxQoygJgpyesehBmKvVu2tCD8y l4TA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703005269; x=1703610069; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tvxDLNOYjKdWlkXmI7fVu1cGUQmdpgYMh9GlbetV5JM=; b=wFVchY4bumpzVka9ynjajLQYxeKuD9Q95LnlnFUoDlxYvWQDlA8LHgDOl821lRM4n+ If3wGPqnH4P8Z3dtOIv2W4ERrZ/Pmt+Zdau3Glv3fe85OVn5z+SZ1qD1KXVwEc+kfGHG NYcAmzpEKwJtgIbDKOH05HYq3M646rAcXq8ufPn9JQ4Ze2pjdba6Lae8Jhy79w6rEhg9 aIdFcNMyossnqhM3O1QSUBSppymJg4webSYD2C/EmWSlQlqTfMq4K0dGasIVySpPFKpx 9CScz7G0wWsLambMQEgzm7l2gPhaWcR1OKyXV0738SpM+r6YNiUOBJqK8H2f6+3DxFbp OaVQ== X-Gm-Message-State: AOJu0YzA2+oTDqMd+VmZ3Suns+fPdjI7Xf1+Bm92hVOLWKcNpQ3nUjer xRxk2d4Q7yuTGp6qIW7fCA== X-Google-Smtp-Source: AGHT+IGsWNsaajXe5v4hjIqM1EZLyrRrx1NOmjW0Jf66/vPQv93o4u79++vXB9ZEkUXdq2ViVM1Bow== X-Received: by 2002:a05:600c:1d1f:b0:40c:f7b:67e5 with SMTP id l31-20020a05600c1d1f00b0040c0f7b67e5mr8969956wms.37.1703005268722; Tue, 19 Dec 2023 09:01:08 -0800 (PST) Received: from U4.lan ([2a02:810b:f40:4300:7ae5:3e:d1c6:a138]) by smtp.gmail.com with ESMTPSA id i7-20020a05600c354700b0040d2805d158sm3225878wmq.48.2023.12.19.09.01.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 09:01:08 -0800 (PST) From: Alex Bee To: Sandy Huang , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: David Airlie , Daniel Vetter , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Alex Bee Subject: [PATCH v3 02/29] drm/rockchip: vop: Add output selection registers for RK312x Date: Tue, 19 Dec 2023 18:00:32 +0100 Message-ID: <20231219170100.188800-3-knaerzche@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231219170100.188800-1-knaerzche@gmail.com> References: <20231219170100.188800-1-knaerzche@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit In contrast to RK3036, RK312x SoCs have multiple output channels such as RGB (i.e. LVDS TTL), LVDS, DSI and HDMI. In order to support that, this splits output from RK3036 and defines an separate one for RK3126 with the registers required to enable the appropriate output and setup the correct polarity. Signed-off-by: Alex Bee --- changes in v2: - rephrase commit message changes in v3: - none drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 13 ++++++++++++- drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 3 +++ 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c index c51ca82320cb..b9ee02061d5b 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -227,11 +227,22 @@ static const struct vop_win_data rk3126_vop_win_data[] = { .type = DRM_PLANE_TYPE_CURSOR }, }; +static const struct vop_output rk3126_output = { + .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), + .hdmi_pin_pol = VOP_REG(RK3126_INT_SCALER, 0x7, 4), + .hdmi_en = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 22), + .hdmi_dclk_pol = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 23), + .rgb_en = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 24), + .rgb_dclk_pol = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 25), + .mipi_en = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 28), + .mipi_dclk_pol = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 29), +}; + static const struct vop_data rk3126_vop = { .intr = &rk3036_intr, .common = &rk3036_common, .modeset = &rk3036_modeset, - .output = &rk3036_output, + .output = &rk3126_output, .win = rk3126_vop_win_data, .win_size = ARRAY_SIZE(rk3126_vop_win_data), .max_output = { 1920, 1080 }, diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h index 406e981c75bd..fbf1bcc68625 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h @@ -872,6 +872,9 @@ /* rk3036 register definition end */ /* rk3126 register definition */ +#define RK3126_INT_SCALER 0x0c + +/* win1 register */ #define RK3126_WIN1_MST 0x4c #define RK3126_WIN1_DSP_INFO 0x50 #define RK3126_WIN1_DSP_ST 0x54 -- 2.43.0