From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C5D041BC36; Mon, 15 Jan 2024 23:24:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="t+IFcWzB" Received: by smtp.kernel.org (Postfix) with ESMTPSA id ECE4BC43390; Mon, 15 Jan 2024 23:24:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1705361043; bh=8ec++whlYR1eYM36jqi2vAPcu4JKlNRIurHaykpqnWI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=t+IFcWzBUVxsW+qZag54aOIjO2AfptR12H3em+erEMA4Owxk+VBk/ybvYs4a/6wLO lS+cbkilKx0sqKqWksE5jq9gez0PAe20Y9QO20GOs38NRh32WGWVBQXS89+HHTnPM6 590UnyeCkvlnPPUyciWUs7FFHOfh3RptSxoQf/y3Ub+JChKLLtAGl05+Vh19MbqSTp xtMySwZSRZ0W6i8Uovv9PrniOWwzU9Z4FCSHi5u4uEF9y26xGPacJ326zwgkVsJ/Tr KfUzz2q3HOr7UrPWzaMZssHzMQ32pp4hBpuIe0jZiX7P1muG1yk0D0fqiTzat1T71m dUWmHZlaHkmhg== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Mark Rutland , Will Deacon , Sasha Levin , linux-arm-kernel@lists.infradead.org Subject: [PATCH AUTOSEL 6.7 05/14] drivers/perf: pmuv3: don't expose SW_INCR event in sysfs Date: Mon, 15 Jan 2024 18:23:19 -0500 Message-ID: <20240115232351.208489-5-sashal@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240115232351.208489-1-sashal@kernel.org> References: <20240115232351.208489-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 6.7 Content-Transfer-Encoding: 8bit From: Mark Rutland [ Upstream commit ca6f537e459e2da4b331fe8928d1a0b0f9301f42 ] The SW_INCR event is somewhat unusual, and depends on the specific HW counter that it is programmed into. When programmed into PMEVCNTR, SW_INCR will count any writes to PMSWINC_EL0 with bit n set, ignoring writes to SW_INCR with bit n clear. Event rotation means that there's no fixed relationship between perf_events and HW counters, so this isn't all that useful. Further, we program PMUSERENR.{SW,EN}=={0,0}, which causes EL0 writes to PMSWINC_EL0 to be trapped and handled as UNDEFINED, resulting in a SIGILL to userspace. Given that, it's not a good idea to expose SW_INCR in sysfs. Hide it as we did for CHAIN back in commit: 4ba2578fa7b55701 ("arm64: perf: don't expose CHAIN event in sysfs") Signed-off-by: Mark Rutland Cc: Will Deacon Link: https://lore.kernel.org/r/20231204115847.2993026-1-mark.rutland@arm.com Signed-off-by: Will Deacon Signed-off-by: Sasha Levin --- drivers/perf/arm_pmuv3.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c index 6ca7be05229c..0e80fdc9f9ca 100644 --- a/drivers/perf/arm_pmuv3.c +++ b/drivers/perf/arm_pmuv3.c @@ -169,7 +169,11 @@ armv8pmu_events_sysfs_show(struct device *dev, PMU_EVENT_ATTR_ID(name, armv8pmu_events_sysfs_show, config) static struct attribute *armv8_pmuv3_event_attrs[] = { - ARMV8_EVENT_ATTR(sw_incr, ARMV8_PMUV3_PERFCTR_SW_INCR), + /* + * Don't expose the sw_incr event in /sys. It's not usable as writes to + * PMSWINC_EL0 will trap as PMUSERENR.{SW,EN}=={0,0} and event rotation + * means we don't have a fixed event<->counter relationship regardless. + */ ARMV8_EVENT_ATTR(l1i_cache_refill, ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL), ARMV8_EVENT_ATTR(l1i_tlb_refill, ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL), ARMV8_EVENT_ATTR(l1d_cache_refill, ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL), -- 2.43.0