[PATCH AUTOSEL 6.7 108/108] ARM: dts: usr8200: Fix phy registers

Sasha Levin
2024-01-16T19:47:09Z

From: Linus Walleij <linus.walleij@linaro.org>

[ Upstream commit 18a1ee9d716d355361da2765f87dbbadcdea03bf ]

The MV88E6060 switch has internal PHY registers at MDIO
addresses 0x00..0x04. Tie each port to the corresponding
PHY.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20231020-ixp4xx-usr8200-dtsfix-v1-1-3a8591dea259@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
.../ixp/intel-ixp42x-usrobotics-usr8200.dts | 22 +++++++++++++++++++
1 file changed, 22 insertions(+)

diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts
index 90fd51b36e7d..2c89db34c8d8 100644
--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts
+++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts
@@ -165,6 +165,24 @@ mdio {
#address-cells = <1>;
#size-cells = <0>;

+ /*
+ * PHY 0..4 are internal to the MV88E6060 switch but appear
+ * as independent devices.
+ */
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+ phy2: ethernet-phy@2 {
+ reg = <2>;
+ };
+ phy3: ethernet-phy@3 {
+ reg = <3>;
+ };
+
+ /* Altima AMI101L used by the WAN port */
phy9: ethernet-phy@9 {
reg = <9>;
};
@@ -181,21 +199,25 @@ ports {
port@0 {
reg = <0>;
label = "lan1";
+ phy-handle = <&phy0>;
};

port@1 {
reg = <1>;
label = "lan2";
+ phy-handle = <&phy1>;
};

port@2 {
reg = <2>;
label = "lan3";
+ phy-handle = <&phy2>;
};

port@3 {
reg = <3>;
label = "lan4";
+ phy-handle = <&phy3>;
};

port@5 {
--
2.43.0