From: Thomas Gleixner <tglx@linutronix.de>
To: LKML <linux-kernel@vger.kernel.org>
Cc: x86@kernel.org, Tom Lendacky <thomas.lendacky@amd.com>,
Andrew Cooper <andrew.cooper3@citrix.com>,
Arjan van de Ven <arjan@linux.intel.com>,
Huang Rui <ray.huang@amd.com>, Juergen Gross <jgross@suse.com>,
Dimitri Sivanich <dimitri.sivanich@hpe.com>,
Sohil Mehta <sohil.mehta@intel.com>,
K Prateek Nayak <kprateek.nayak@amd.com>,
Kan Liang <kan.liang@linux.intel.com>,
Zhang Rui <rui.zhang@intel.com>,
"Paul E. McKenney" <paulmck@kernel.org>,
Feng Tang <feng.tang@intel.com>,
Andy Shevchenko <andy@infradead.org>,
Michael Kelley <mhklinux@outlook.com>,
"Peter Zijlstra (Intel)" <peterz@infradead.org>,
Andy Shevchenko <andy.shevchenko@gmail.com>,
Wei Liu <wei.liu@kernel.org>
Subject: [patch V2 01/22] x86/cpu/topology: Make the APIC mismatch warnings complete
Date: Tue, 23 Jan 2024 14:10:04 +0100 (CET) [thread overview]
Message-ID: <20240117124902.403342409@linutronix.de> (raw)
In-Reply-To: 20240117124704.044462658@linutronix.de
From: Thomas Gleixner <tglx@linutronix.de>
Detect all possible combinations of mismatch right in the CPUID evaluation
code.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
arch/x86/include/asm/apic.h | 5 ++---
arch/x86/kernel/cpu/common.c | 15 ++-------------
arch/x86/kernel/cpu/topology_common.c | 12 ++++++++++++
3 files changed, 16 insertions(+), 16 deletions(-)
---
--- a/arch/x86/include/asm/apic.h
+++ b/arch/x86/include/asm/apic.h
@@ -46,16 +46,15 @@ extern void x86_32_probe_apic(void);
static inline void x86_32_probe_apic(void) { }
#endif
-#ifdef CONFIG_X86_LOCAL_APIC
+extern u32 cpuid_to_apicid[];
+#ifdef CONFIG_X86_LOCAL_APIC
extern int apic_verbosity;
extern int local_apic_timer_c2_ok;
extern bool apic_is_disabled;
extern unsigned int lapic_timer_period;
-extern u32 cpuid_to_apicid[];
-
extern enum apic_intr_mode_id apic_intr_mode;
enum apic_intr_mode_id {
APIC_PIC,
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -1715,22 +1715,11 @@ static void generic_identify(struct cpui
#endif
}
-/*
- * Validate that ACPI/mptables have the same information about the
- * effective APIC id and update the package map.
- */
-static void validate_apic_and_package_id(struct cpuinfo_x86 *c)
+static void update_package_map(struct cpuinfo_x86 *c)
{
#ifdef CONFIG_SMP
unsigned int cpu = smp_processor_id();
- u32 apicid;
- apicid = apic->cpu_present_to_apicid(cpu);
-
- if (apicid != c->topo.apicid) {
- pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n",
- cpu, apicid, c->topo.initial_apicid);
- }
BUG_ON(topology_update_package_map(c->topo.pkg_id, cpu));
BUG_ON(topology_update_die_map(c->topo.die_id, cpu));
#else
@@ -1921,7 +1910,7 @@ void identify_secondary_cpu(struct cpuin
#ifdef CONFIG_X86_32
enable_sep_cpu();
#endif
- validate_apic_and_package_id(c);
+ update_package_map(c);
x86_spec_ctrl_setup_ap();
update_srbds_msr();
if (boot_cpu_has_bug(X86_BUG_GDS))
--- a/arch/x86/kernel/cpu/topology_common.c
+++ b/arch/x86/kernel/cpu/topology_common.c
@@ -177,6 +177,18 @@ void cpu_parse_topology(struct cpuinfo_x
parse_topology(&tscan, false);
+ if (IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
+ if (c->topo.initial_apicid != c->topo.apicid) {
+ pr_err(FW_BUG "CPU%4u: APIC ID mismatch. CPUID: 0x%04x APIC: 0x%04x\n",
+ cpu, c->topo.initial_apicid, c->topo.apicid);
+ }
+
+ if (c->topo.apicid != cpuid_to_apicid[cpu]) {
+ pr_err(FW_BUG "CPU%4u: APIC ID mismatch. Firmware: 0x%04x APIC: 0x%04x\n",
+ cpu, cpuid_to_apicid[cpu], c->topo.apicid);
+ }
+ }
+
for (dom = TOPO_SMT_DOMAIN; dom < TOPO_MAX_DOMAIN; dom++) {
if (tscan.dom_shifts[dom] == x86_topo_system.dom_shifts[dom])
continue;
next prev parent reply other threads:[~2024-01-23 13:10 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-23 13:10 [patch V2 00/22] x86/topology: More cleanups and preparatory work Thomas Gleixner
2024-01-23 13:10 ` Thomas Gleixner [this message]
2024-01-25 9:53 ` [patch V2 01/22] x86/cpu/topology: Make the APIC mismatch warnings complete Ashok Raj
2024-02-12 15:39 ` Thomas Gleixner
2024-01-23 13:10 ` [patch V2 02/22] x86/platform/ce4100: Dont override x86_init.mpparse.setup_ioapic_ids Thomas Gleixner
2024-01-23 13:10 ` [patch V2 03/22] x86/ioapic: Replace some more set bit nonsense Thomas Gleixner
2024-01-23 13:10 ` [patch V2 04/22] x86/apic: Get rid of get_physical_broadcast() Thomas Gleixner
2024-02-01 22:24 ` Sohil Mehta
2024-01-23 13:10 ` [patch V2 05/22] x86/ioapic: Make io_apic_get_unique_id() simpler Thomas Gleixner
2024-01-23 13:10 ` [patch V2 06/22] x86/ioapic: Simplify setup_ioapic_ids_from_mpc_nocheck() Thomas Gleixner
2024-01-23 13:10 ` [patch V2 07/22] x86/apic: Remove check_apicid_used() and ioapic_phys_id_map() Thomas Gleixner
2024-01-23 13:10 ` [patch V2 08/22] x86/mpparse: Rename default_find_smp_config() Thomas Gleixner
2024-01-23 13:10 ` [patch V2 09/22] x86/mpparse: Provide separate early/late callbacks Thomas Gleixner
2024-01-23 13:10 ` [patch V2 10/22] x86/mpparse: Prepare for callback separation Thomas Gleixner
2024-01-23 13:10 ` [patch V2 11/22] x86/dtb: Rename x86_dtb_init() Thomas Gleixner
2024-01-23 13:10 ` [patch V2 12/22] x86/platform/ce4100: Prepare for separate mpparse callbacks Thomas Gleixner
2024-01-23 13:10 ` [patch V2 13/22] x86/platform/intel-mid: " Thomas Gleixner
2024-01-23 13:10 ` [patch V2 14/22] x86/jailhouse: " Thomas Gleixner
2024-01-23 13:10 ` [patch V2 15/22] x86/xen/smp_pv: " Thomas Gleixner
2024-01-23 13:10 ` [patch V2 16/22] x86/hyperv/vtl: " Thomas Gleixner
2024-01-23 13:10 ` [patch V2 17/22] x86/mpparse: Switch to new init callbacks Thomas Gleixner
2024-01-23 13:10 ` [patch V2 18/22] x86/mm/numa: Move early mptable evaluation into common code Thomas Gleixner
2024-01-23 13:10 ` [patch V2 19/22] x86/mpparse: Remove the physid_t bitmap wrapper Thomas Gleixner
2024-01-23 13:10 ` [patch V2 20/22] x86/apic: Remove the pointless writeback of boot_cpu_physical_apicid Thomas Gleixner
2024-01-23 13:10 ` [patch V2 21/22] x86/apic: Remove yet another dubious callback Thomas Gleixner
2024-01-23 13:10 ` [patch V2 22/22] x86/apic: Use a proper define for invalid ACPI CPU ID Thomas Gleixner
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