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Mon, 22 Jan 2024 09:21:51 -0800 (PST) X-Google-Smtp-Source: AGHT+IF22UHtqop2p9ldWS0FUSCe44a8uIXyYTv6zwTkEm4KTH9So+jKN01poJ3m4ghRt3Y9yA0QGA== X-Received: by 2002:a05:6122:179c:b0:4b7:422b:d7c3 with SMTP id o28-20020a056122179c00b004b7422bd7c3mr1787474vkf.20.1705944111456; Mon, 22 Jan 2024 09:21:51 -0800 (PST) Received: from [192.168.1.163] ([2600:1700:1ff0:d0e0::37]) by smtp.gmail.com with ESMTPSA id lf3-20020a0562142cc300b00680c25f5f06sm2567738qvb.86.2024.01.22.09.21.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jan 2024 09:21:47 -0800 (PST) From: Andrew Halaney Date: Mon, 22 Jan 2024 11:21:30 -0600 Subject: [PATCH RFC v4 05/11] scsi: ufs: qcom: Perform read back after writing CGC enable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20240122-ufs-reset-ensure-effect-before-delay-v4-5-6c48432151cc@redhat.com> References: <20240122-ufs-reset-ensure-effect-before-delay-v4-0-6c48432151cc@redhat.com> In-Reply-To: <20240122-ufs-reset-ensure-effect-before-delay-v4-0-6c48432151cc@redhat.com> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Manivannan Sadhasivam , "James E.J. Bottomley" , "Martin K. Petersen" , Hannes Reinecke , Janek Kotas , Alim Akhtar , Avri Altman , Bart Van Assche , Can Guo Cc: Will Deacon , linux-arm-msm@vger.kernel.org, linux-scsi@vger.kernel.org, linux-kernel@vger.kernel.org, Andrew Halaney , Manivannan Sadhasivam X-Mailer: b4 0.12.3 Currently, the CGC enable bit is written and then an mb() is used to ensure that completes before continuing. mb() ensure that the write completes, but completion doesn't mean that it isn't stored in a buffer somewhere. The recommendation for ensuring this bit has taken effect on the device is to perform a read back to force it to make it all the way to the device. This is documented in device-io.rst and a talk by Will Deacon on this can be seen over here: https://youtu.be/i6DayghhA8Q?si=MiyxB5cKJXSaoc01&t=1678 Let's do that to ensure the bit hits the device. Because the mb()'s purpose wasn't to add extra ordering (on top of the ordering guaranteed by writel()/readl()), it can safely be removed. Reviewed-by: Manivannan Sadhasivam Reviewed-by: Can Guo Fixes: 81c0fc51b7a7 ("ufs-qcom: add support for Qualcomm Technologies Inc platforms") Signed-off-by: Andrew Halaney --- drivers/ufs/host/ufs-qcom.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index decad95bd444..881074fc2329 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -406,7 +406,7 @@ static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba) REG_UFS_CFG2); /* Ensure that HW clock gating is enabled before next operations */ - mb(); + ufshcd_readl(hba, REG_UFS_CFG2); } static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba, -- 2.43.0