[PATCH v3 0/5] Add CPSW2G and CPSW9G nodes for J784S4

Chintan Vankar
2024-01-25T10:05:53Z

This series adds device-tree nodes for CPSW2G and CPSW9G instance
of the CPSW Ethernet Switch on TI's J784S4 SoC. Additionally,
two device-tree overlays are also added:
1. QSGMII mode with the CPSW9G instance via the ENET EXPANSION 1
connector.
2. USXGMII mode with MAC Ports 1 and 2 of the CPSW9G instance via
ENET EXPANSION 1 and 2 connectors, configured in fixed-link
mode of operation at 5Gbps link speed.

Similar to Andrew Davis patch at:
https://lore.kernel.org/r/20231117222930.228688-5-afd@ti.com/ for J721E,
similar changes are also required for J784S4 to remove dependency on the
parent node being a syscon node.

This series combines the v1 series at:
https://lore.kernel.org/r/20230522092201.127598-1-s-vadapalli@ti.com/
and the patch for Main CPSW2G node that is present in [PATCH v6 2/5] at:
https://lore.kernel.org/r/20230721132029.123881-1-j-choudhary@ti.com/
but dropped in it's next version at:
https://lore.kernel.org/r/20231019054022.175163-1-j-choudhary@ti.com/

Changes from v1 for J784S4 CPSW9G DT Support:
1. Update serdes_ln_ctrl node in k3-j784s4-main.dtsi
to remove dependency on the parent node being a syscon node.
2. The patch for Main CPSW2G node is combined.
3. Update description in k3-j784s4-evm-quad-port-eth-exp1.dtso
QSGMII overlay file and add product link for QSGMII
daughtercard.
4. Add a comment in k3-j784s4-evm-usxgmii-exp1-exp2.dtso
USXGMII overlay file for the serdes_wiz2 node since it uses
156.25 MHz clock for USXGMII.

Changes from v6 for J784S4 Main CPSW2G node:
1. Rename node name in k3-j784s4-main.dtsi from
main_cpsw2g_pins_default to main_cpsw2g_default_pins,
main_cpsw2g_mdio_pins_default to main_cpsw2g_mdio_default_pins
and main_phy0 to main_cpsw1_phy0 based on Tony's suggestion at:
https://lore.kernel.org/all/20230724045032.GU5194@atomide.com/

Chintan Vankar (1):
arm64: dts: ti: k3-j784s4-main: Fix mux-reg-masks in serdes_ln_ctrl

Siddharth Vadapalli (4):
arm64: dts: ti: k3-j784s4-main: Add CPSW2G and CPSW9G nodes
arm64: dts: ti: k3-j784s4: Add Main CPSW2G node
arm64: dts: ti: k3-j784s4: Add overlay to enable QSGMII mode with
CPSW9G
arm64: dts: ti: k3-j784s4: Add overlay for dual port USXGMII mode

arch/arm64/boot/dts/ti/Makefile | 11 +-
.../ti/k3-j784s4-evm-quad-port-eth-exp1.dtso | 146 +++++++++++++
.../ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso | 73 +++++++
arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 47 +++++
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 194 +++++++++++++++++-
5 files changed, 464 insertions(+), 7 deletions(-)
create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso
create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso

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2.34.1