Re: [PATCH v3 1/2] perf/marvell: Odyssey DDR Performance monitor support

[kernel test robot <lkp@intel.com>]

Hi Gowthami,

kernel test robot noticed the following build warnings:

[auto build test WARNING on soc/for-next]
[also build test WARNING on linus/master v6.8-rc1 next-20240125]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Gowthami-Thiagarajan/perf-marvell-Odyssey-DDR-Performance-monitor-support/20240122-205209
base:   https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git for-next
patch link:    https://lore.kernel.org/r/20240122124933.1311925-2-gthiagarajan%40marvell.com
patch subject: [PATCH v3 1/2] perf/marvell: Odyssey DDR Performance monitor support
config: s390-allmodconfig (https://download.01.org/0day-ci/archive/20240126/202401261154.gKVsomua-lkp@intel.com/config)
compiler: s390-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240126/202401261154.gKVsomua-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202401261154.gKVsomua-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/perf/marvell_cn10k_ddr_pmu.c:195:43: warning: 'odyssey_ddr_pmu_pdata' defined but not used [-Wunused-const-variable=]
     195 | static const struct ddr_pmu_platform_data odyssey_ddr_pmu_pdata = {
         |                                           ^~~~~~~~~~~~~~~~~~~~~


vim +/odyssey_ddr_pmu_pdata +195 drivers/perf/marvell_cn10k_ddr_pmu.c

   194	
 > 195	static const struct ddr_pmu_platform_data odyssey_ddr_pmu_pdata = {
   196		.counter_overflow_val = 0,
   197		.counter_max_val = GENMASK_ULL(63, 0),
   198		.ddrc_perf_cnt_base = ODY_DDRC_PERF_CNT_VALUE_BASE,
   199		.ddrc_perf_cfg_base = ODY_DDRC_PERF_CFG_BASE,
   200		.ddrc_perf_cnt_op_mode_ctrl = ODY_DDRC_PERF_CNT_OP_MODE_CTRL,
   201		.ddrc_perf_cnt_start_op_ctrl = ODY_DDRC_PERF_CNT_START_OP_CTRL,
   202		.ddrc_perf_cnt_end_op_ctrl = ODY_DDRC_PERF_CNT_END_OP_CTRL,
   203		.ddrc_perf_cnt_end_status = ODY_DDRC_PERF_CNT_END_STATUS,
   204		.ddrc_perf_cnt_freerun_en = 0,
   205		.ddrc_perf_cnt_freerun_ctrl = ODY_DDRC_PERF_CNT_FREERUN_CTRL,
   206		.ddrc_perf_cnt_freerun_clr = ODY_DDRC_PERF_CNT_FREERUN_CLR,
   207		.ddrc_perf_cnt_value_wr_op = ODY_DDRC_PERF_CNT_VALUE_WR_OP,
   208		.ddrc_perf_cnt_value_rd_op = ODY_DDRC_PERF_CNT_VALUE_RD_OP,
   209	};
   210	

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