Re: [PATCH v6 6/6] PCI: qcom: Add OPP support to scale performance state of power domain

Krishna Chaitanya Chundru
2024-01-16T05:19:18Z

On 1/13/2024 4:14 AM, Konrad Dybcio wrote:
> On 12.01.2024 15:22, Krishna chaitanya chundru wrote:
>> QCOM Resource Power Manager-hardened (RPMh) is a hardware block which
>> maintains hardware state of a regulator by performing max aggregation of
>> the requests made by all of the processors.
>>
>> PCIe controller can operate on different RPMh performance state of power
>> domain based up on the speed of the link. And this performance state varies
>> from target to target.
>>
>> It is manadate to scale the performance state based up on the PCIe speed
>> link operates so that SoC can run under optimum power conditions.
>>
>> Add Operating Performance Points(OPP) support to vote for RPMh state based
>> upon GEN speed link is operating.
>>
>> OPP can handle ICC bw voting also, so move icc bw voting through opp
>> framework if opp entries are present.
>>
>> In PCIe certain gen speeds like GEN1x2 & GEN2X1 or GEN3x2 & GEN4x1 use
>> same icc bw and has frequency, so use frequency based search to reduce
>> number of entries in the opp table.
>>
>> Don't initialize icc if opp is supported.
>>
>> Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
>> ---
>
> [...]
>
>>
>> -static void qcom_pcie_icc_update(struct qcom_pcie *pcie)
>> +static void qcom_pcie_icc_opp_update(struct qcom_pcie *pcie)
>
> Or simply.. qcom_pcie_opp_update :) Especially with Dmitry's
> suggestions
>
If OPP path is not present we are still voting through ICC, so it is
better to have name as it.
>> {
>> struct dw_pcie *pci = pcie->pci;
>> - u32 offset, status;
>> + u32 offset, status, freq;
>> + struct dev_pm_opp *opp;
>> int speed, width;
>> int ret;
>>
>> - if (!pcie->icc_mem)
>> - return;
>> -
>> offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
>> status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA);
>>
>> @@ -1424,11 +1424,42 @@ static void qcom_pcie_icc_update(struct qcom_pcie *pcie)
>> speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status);
>> width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status);
>>
>> - ret = icc_set_bw(pcie->icc_mem, 0, width * QCOM_PCIE_LINK_SPEED_TO_BW(speed));
>> - if (ret) {
>> - dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
>> - ret);
>> + if (pcie->opp_supported) {
>> + switch (speed) {
>> + case 1:
>> + freq = 2500000;
>> + break;
>> + case 2:
>> + freq = 5000000;
>> + break;
>> + case 3:
>> + freq = 8000000;
>> + break;
>> + default:
>> + WARN_ON_ONCE(1);
>> + fallthrough;
>> + case 4:
>> + freq = 16000000;
>> + break;
>> + }
> Might as well add gen5 and 6 rates of 3200.. and 6400.. since they're
> hard-in-stone in the spec by now, AFAIK
>
> Konrad
ACK.

- Krishna Chaitanya.