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Mon, 05 Feb 2024 09:20:31 -0800 (PST) From: Anand Moon To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: Anand Moon , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCHv1 3/5] arm64: dts: amlogic: Add cache information to the Amlogic G12A SoCS Date: Mon, 5 Feb 2024 22:49:21 +0530 Message-ID: <20240205171930.968-4-linux.amoon@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240205171930.968-1-linux.amoon@gmail.com> References: <20240205171930.968-1-linux.amoon@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit As per the S905X2 datasheet add missing cache information to the Amlogic G12A SoC. - Each Cortex-A53 core has 32KB of L1 instruction cache available and 32KB of L1 data cache available. - Along with 512KB Unified L2 cache. To improve system performance. Signed-off-by: Anand Moon --- No public dataheet available, since S905X2 support Arm Cortex-A53 cpu nence used the same cache size as S905 and S905X. --- arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 27 +++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi index 543e70669df5..6e1e3a3f5f18 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi @@ -17,6 +17,12 @@ cpu0: cpu@0 { compatible = "arm,cortex-a53"; reg = <0x0 0x0>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; #cooling-cells = <2>; }; @@ -26,6 +32,12 @@ cpu1: cpu@1 { compatible = "arm,cortex-a53"; reg = <0x0 0x1>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; #cooling-cells = <2>; }; @@ -35,6 +47,12 @@ cpu2: cpu@2 { compatible = "arm,cortex-a53"; reg = <0x0 0x2>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; #cooling-cells = <2>; }; @@ -44,6 +62,12 @@ cpu3: cpu@3 { compatible = "arm,cortex-a53"; reg = <0x0 0x3>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; #cooling-cells = <2>; }; @@ -52,6 +76,9 @@ l2: l2-cache0 { compatible = "cache"; cache-level = <2>; cache-unified; + cache-size = <0x7d000>; /* L2. 512 KB */ + cache-line-size = <64>; + cache-sets = <512>; }; }; -- 2.43.0