From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 65CF61386CB; Wed, 7 Feb 2024 21:22:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707340954; cv=none; b=ujlI2VTPxgnTqWsEgip1WyYa28TeBRPMg8muNxPwgGmCp29DFJZeyprNdYBwfgTmIeIt8jKOeqJ8qLvTQ96RAajKCUL/3xY7VVCgz6or3FBloPZoUkp0ILPsAmaJynoihAHkGazzaXUp+wz/RJ4izOLy4sMTb7RnFKLf7MYX4s0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707340954; c=relaxed/simple; bh=HypDdf2hjjBPIzrRj27Vpyxm10qBsZQ3coQ3zvmXXOo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uK7QntLf7ew3VtL5Kcl+cjV1i9vpjHbYz1h62CLPE3s4KlnBe+Y6pnABeITID4sduAnz0xh6vIbUQsCiTcFUosA3578bY+SqLGmcN5kEmBDHJi/8v2Qpq2//2JypI+Z7f7Y5YC/3+yB1PRXR0AKLWaDnHbY2K9Xc0EJ3hgNqe/g= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=lpyiX8iK; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lpyiX8iK" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6808FC433F1; Wed, 7 Feb 2024 21:22:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1707340953; bh=HypDdf2hjjBPIzrRj27Vpyxm10qBsZQ3coQ3zvmXXOo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lpyiX8iKYCtZuu5CGCqKkaN5b41tB9bg334Y76JV7r1+wdyd9L+aWCaJhmPHFLrRv FDj2lpQfYEtT7i/8SdYkfgIP0nYBJurDBh4h/P0RrmI047EKVjmbO2ZK2VClBMAMRE GcV9rUx/W550XUv2EVoWMwVBbqMosL9ND55+b3XHNV8N3NbvgXS59/hFYNJyQOp6BR XwEK4PpLTSt4O5b9+6H9YkBfPKJEIKjjy6oxQYY5hY4q9qLdkMfLJWktkRxn3Ws9PB cWcmpXbAsMXT86EZ6b7MIma4ZTttewmZmHibnFg90v0rR7rwg83goN7Pl4Hv4uPsF1 ardprOovKwUlg== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Sohaib Nadeem , Chaitanya Dhere , Alvin Lee , Tom Chung , Daniel Wheeler , Alex Deucher , Sasha Levin , harry.wentland@amd.com, sunpeng.li@amd.com, Rodrigo.Siqueira@amd.com, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch, jun.lei@amd.com, wenjing.liu@amd.com, austin.zheng@amd.com, Qingqing.Zhuo@amd.com, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH AUTOSEL 6.7 25/44] drm/amd/display: increased min_dcfclk_mhz and min_fclk_mhz Date: Wed, 7 Feb 2024 16:20:52 -0500 Message-ID: <20240207212142.1399-25-sashal@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240207212142.1399-1-sashal@kernel.org> References: <20240207212142.1399-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 6.7.4 Content-Transfer-Encoding: 8bit From: Sohaib Nadeem [ Upstream commit 2ff33c759a4247c84ec0b7815f1f223e155ba82a ] [why] Originally, PMFW said min FCLK is 300Mhz, but min DCFCLK can be increased to 400Mhz because min FCLK is now 600Mhz so FCLK >= 1.5 * DCFCLK hardware requirement will still be satisfied. Increasing min DCFCLK addresses underflow issues (underflow occurs when phantom pipe is turned on for some Sub-Viewport configs). [how] Increasing DCFCLK by raising the min_dcfclk_mhz Reviewed-by: Chaitanya Dhere Reviewed-by: Alvin Lee Acked-by: Tom Chung Signed-off-by: Sohaib Nadeem Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c index 92e2ddc9ab7e..67497d7d66d2 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c @@ -2719,7 +2719,7 @@ static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk struct _vcs_dpi_voltage_scaling_st entry = {0}; struct clk_limit_table_entry max_clk_data = {0}; - unsigned int min_dcfclk_mhz = 199, min_fclk_mhz = 299; + unsigned int min_dcfclk_mhz = 399, min_fclk_mhz = 599; static const unsigned int num_dcfclk_stas = 5; unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564}; -- 2.43.0