From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0110B128389; Wed, 7 Feb 2024 21:24:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707341054; cv=none; b=W2Ra025nMU96rCNJ3u1EqztcB25DJUsB7XbSudtJ8Ossa3+xOTZISh79o7rmWgcHuYMpnFF9Kn4nJKz6hoXAQyxhzYEq/rhDIwAcGv4cZ2YwqNKleuRuNyGJ7czLSP438Qynyq6iH9eaWPfGuPQKPI0R8F2KAZNw+DtpeImSmF4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707341054; c=relaxed/simple; bh=iKLsFpxZAKXdU3Dh4xq8EBlGqQ0v28uGCDiERYwasto=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=eC9OKOMDTao8oZGxzJXjmu4aHVH+4Gx9jIdA3lSUpyDQAaSSQnaDgcLeaTW+VpOD6rEIcCl2k8p4KH6OU502iu4SXfyZS5rJ7WUynTlX+QdiPh+xnAJlIq/pR6NrvC+YGehrakdE5Ff1Lx1RBuCIKbedWjje1qbYuXU2dSOS4Ss= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=A0txqz+g; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="A0txqz+g" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7F9AEC433C7; Wed, 7 Feb 2024 21:24:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1707341053; bh=iKLsFpxZAKXdU3Dh4xq8EBlGqQ0v28uGCDiERYwasto=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=A0txqz+gb0raufqbTyR6B0tBX9g9bMSohqCJGt8vqXgT75HqoZwKr+Qp8z7Z/9ztW Dq13xeWWs/iAePnGQL8cjIR7VsBQlwo7Z5VKXRCOwnWATqZOzbc8G3Ajj70FeXumhk 0i84X+k4k7atTWMNvA0IUnXJgo1kO1VzA0KTav/zvYFc0UR0BVfO8tFp4KCmsfHrye bU9u+x/3MkWT6AepEUnlp6oQEgTl0k3ULauCqc/Q4cKgwX7ljuYOzKk2IOuhMNDGx0 2qlnNDPuXONa+9+aplFx+cgHKJ7A9uTMg2BYLmjd3uPTV+uW5XcVzkw7e87FEcCWvl xCEajBct7V1QQ== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Wolfram Sang , Geert Uytterhoeven , Mark Brown , Sasha Levin , linux-spi@vger.kernel.org Subject: [PATCH AUTOSEL 6.6 18/38] spi: sh-msiof: avoid integer overflow in constants Date: Wed, 7 Feb 2024 16:23:04 -0500 Message-ID: <20240207212337.2351-18-sashal@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240207212337.2351-1-sashal@kernel.org> References: <20240207212337.2351-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 6.6.16 Content-Transfer-Encoding: 8bit From: Wolfram Sang [ Upstream commit 6500ad28fd5d67d5ca0fee9da73c463090842440 ] cppcheck rightfully warned: drivers/spi/spi-sh-msiof.c:792:28: warning: Signed integer overflow for expression '7<<29'. [integerOverflow] sh_msiof_write(p, SIFCTR, SIFCTR_TFWM_1 | SIFCTR_RFWM_1); Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Link: https://msgid.link/r/20240130094053.10672-1-wsa+renesas@sang-engineering.com Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- drivers/spi/spi-sh-msiof.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c index cfc3b1ddbd22..6f12e4fb2e2e 100644 --- a/drivers/spi/spi-sh-msiof.c +++ b/drivers/spi/spi-sh-msiof.c @@ -136,14 +136,14 @@ struct sh_msiof_spi_priv { /* SIFCTR */ #define SIFCTR_TFWM_MASK GENMASK(31, 29) /* Transmit FIFO Watermark */ -#define SIFCTR_TFWM_64 (0 << 29) /* Transfer Request when 64 empty stages */ -#define SIFCTR_TFWM_32 (1 << 29) /* Transfer Request when 32 empty stages */ -#define SIFCTR_TFWM_24 (2 << 29) /* Transfer Request when 24 empty stages */ -#define SIFCTR_TFWM_16 (3 << 29) /* Transfer Request when 16 empty stages */ -#define SIFCTR_TFWM_12 (4 << 29) /* Transfer Request when 12 empty stages */ -#define SIFCTR_TFWM_8 (5 << 29) /* Transfer Request when 8 empty stages */ -#define SIFCTR_TFWM_4 (6 << 29) /* Transfer Request when 4 empty stages */ -#define SIFCTR_TFWM_1 (7 << 29) /* Transfer Request when 1 empty stage */ +#define SIFCTR_TFWM_64 (0UL << 29) /* Transfer Request when 64 empty stages */ +#define SIFCTR_TFWM_32 (1UL << 29) /* Transfer Request when 32 empty stages */ +#define SIFCTR_TFWM_24 (2UL << 29) /* Transfer Request when 24 empty stages */ +#define SIFCTR_TFWM_16 (3UL << 29) /* Transfer Request when 16 empty stages */ +#define SIFCTR_TFWM_12 (4UL << 29) /* Transfer Request when 12 empty stages */ +#define SIFCTR_TFWM_8 (5UL << 29) /* Transfer Request when 8 empty stages */ +#define SIFCTR_TFWM_4 (6UL << 29) /* Transfer Request when 4 empty stages */ +#define SIFCTR_TFWM_1 (7UL << 29) /* Transfer Request when 1 empty stage */ #define SIFCTR_TFUA_MASK GENMASK(26, 20) /* Transmit FIFO Usable Area */ #define SIFCTR_TFUA_SHIFT 20 #define SIFCTR_TFUA(i) ((i) << SIFCTR_TFUA_SHIFT) -- 2.43.0