From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 22FAC1586D7; Wed, 7 Feb 2024 21:25:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707341139; cv=none; b=SNkkMzNpYdQ0n8W2AVb9+HnIcEaegc4gqDbR6k4njfIkD2rbecxbF5QWmRSBn86KGPOx+iaSi8a63L4AWJ1OH/3Xp398HCuC50KJtiarK30WT0YZDPIBY/v15l0FoC1kuLHrPFGQ3FwRM6aYdTvuvvLzewVdqZwnrOUp6iX8ZQs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707341139; c=relaxed/simple; bh=ETw1UgSt30BpklExWxNhFjNShXfG1dH3FHqdG0S9oK8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tm0OA+Fs2SRitNsf5NDfwtREehLFYiE8/jo8MfBQ+ZFRQuZGrj2JrPrjL5eyD1rpwz3XHRN7wEsuYSZLjOUIxZJsdfcy2SXrR2iYXtLGqcO9JQM178KKRfRbiSpn+wm0qaPOQyeyWMkm7jcWjJxbW+VR+1KQNhB5SLhZsmVqK1g= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=UmMaUcaz; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="UmMaUcaz" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 71566C433F1; Wed, 7 Feb 2024 21:25:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1707341139; bh=ETw1UgSt30BpklExWxNhFjNShXfG1dH3FHqdG0S9oK8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UmMaUcaz/aWMfoHPqKtG+bcFVejo5yMCDs5gttUqnk3Bgv2zADzSnmIUVAlaT0+pM Ss+lvzQ3r3X8acnMZHR8g5ifZBioC04NiyAs3LzKXJSQQJoneJpIeomf8nhaKmTuff oj5jTWHAyaued2jlTdXUsbNN58IkdOz/vvArPrhmmBtopvHrDpDfYE6twm8Jq+NoxC zNlBCvS4qfHSFltjwBDZo0G/gBTH14Av0wbajwQLplEN+hJbyxd0TLfocLnZn4iNS2 G7qmfnuz7khD5/P+TeK+9DkrkjJv99S7ZSyTTAskeAi/FRYZ6j/jQ8ybTVAVLTn5yZ /ddodhJosiEWA== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Sohaib Nadeem , Chaitanya Dhere , Alvin Lee , Tom Chung , Daniel Wheeler , Alex Deucher , Sasha Levin , harry.wentland@amd.com, sunpeng.li@amd.com, Rodrigo.Siqueira@amd.com, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch, jun.lei@amd.com, wenjing.liu@amd.com, austin.zheng@amd.com, Qingqing.Zhuo@amd.com, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH AUTOSEL 6.1 16/29] drm/amd/display: increased min_dcfclk_mhz and min_fclk_mhz Date: Wed, 7 Feb 2024 16:24:41 -0500 Message-ID: <20240207212505.3169-16-sashal@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240207212505.3169-1-sashal@kernel.org> References: <20240207212505.3169-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 6.1.77 Content-Transfer-Encoding: 8bit From: Sohaib Nadeem [ Upstream commit 2ff33c759a4247c84ec0b7815f1f223e155ba82a ] [why] Originally, PMFW said min FCLK is 300Mhz, but min DCFCLK can be increased to 400Mhz because min FCLK is now 600Mhz so FCLK >= 1.5 * DCFCLK hardware requirement will still be satisfied. Increasing min DCFCLK addresses underflow issues (underflow occurs when phantom pipe is turned on for some Sub-Viewport configs). [how] Increasing DCFCLK by raising the min_dcfclk_mhz Reviewed-by: Chaitanya Dhere Reviewed-by: Alvin Lee Acked-by: Tom Chung Signed-off-by: Sohaib Nadeem Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c index 85e0d1c2a908..baecc0ffe758 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c @@ -2123,7 +2123,7 @@ static int build_synthetic_soc_states(struct clk_bw_params *bw_params, unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0, max_dtbclk_mhz = 0, max_fclk_mhz = 0, max_uclk_mhz = 0; - unsigned int min_dcfclk_mhz = 199, min_fclk_mhz = 299; + unsigned int min_dcfclk_mhz = 399, min_fclk_mhz = 599; static const unsigned int num_dcfclk_stas = 5; unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564}; -- 2.43.0