From: Eric Chan <ericchancf@google.com>
To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
ericchancf@google.com
Subject: [PATCH v5 4/4] riscv/barrier: Resolve checkpatch.pl error
Date: Tue, 13 Feb 2024 22:40:00 +0000 [thread overview]
Message-ID: <20240213224000.2597959-1-ericchancf@google.com> (raw)
In-Reply-To: <20240213223810.2595804-1-ericchancf@google.com>
The past form of RISCV_FENCE would cause checkpatch.pl to issue
error messages, the example is as follows:
ERROR: space required after that ',' (ctx:VxV)
+#define __atomic_acquire_fence() RISCV_FENCE(r,rw)
^
fix the remaining of RISCV_FENCE.
Signed-off-by: Eric Chan <ericchancf@google.com>
---
arch/riscv/include/asm/barrier.h | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/riscv/include/asm/barrier.h b/arch/riscv/include/asm/barrier.h
index 4f4743d7440d..880b56d8480d 100644
--- a/arch/riscv/include/asm/barrier.h
+++ b/arch/riscv/include/asm/barrier.h
@@ -19,19 +19,19 @@
/* These barriers need to enforce ordering on both devices or memory. */
-#define __mb() RISCV_FENCE(iorw,iorw)
-#define __rmb() RISCV_FENCE(ir,ir)
-#define __wmb() RISCV_FENCE(ow,ow)
+#define __mb() RISCV_FENCE(iorw, iorw)
+#define __rmb() RISCV_FENCE(ir, ir)
+#define __wmb() RISCV_FENCE(ow, ow)
/* These barriers do not need to enforce ordering on devices, just memory. */
-#define __smp_mb() RISCV_FENCE(rw,rw)
-#define __smp_rmb() RISCV_FENCE(r,r)
-#define __smp_wmb() RISCV_FENCE(w,w)
+#define __smp_mb() RISCV_FENCE(rw, rw)
+#define __smp_rmb() RISCV_FENCE(r, r)
+#define __smp_wmb() RISCV_FENCE(w, w)
#define __smp_store_release(p, v) \
do { \
compiletime_assert_atomic_type(*p); \
- RISCV_FENCE(rw,w); \
+ RISCV_FENCE(rw, w); \
WRITE_ONCE(*p, v); \
} while (0)
@@ -39,7 +39,7 @@ do { \
({ \
typeof(*p) ___p1 = READ_ONCE(*p); \
compiletime_assert_atomic_type(*p); \
- RISCV_FENCE(r,rw); \
+ RISCV_FENCE(r, rw); \
___p1; \
})
@@ -68,7 +68,7 @@ do { \
* instances the scheduler pairs this with an mb(), so nothing is necessary on
* the new hart.
*/
-#define smp_mb__after_spinlock() RISCV_FENCE(iorw,iorw)
+#define smp_mb__after_spinlock() RISCV_FENCE(iorw, iorw)
#include <asm-generic/barrier.h>
--
2.43.0.687.g38aa6559b0-goog
next prev parent reply other threads:[~2024-02-13 22:40 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-13 22:38 [PATCH v5 0/4] riscv/barrier: tidying up barrier-related macro Eric Chan
2024-02-13 22:39 ` [PATCH v5 1/4] riscv/barrier: Define __{mb,rmb,wmb} Eric Chan
2024-02-16 20:30 ` Andrea Parri
2024-02-13 22:39 ` [PATCH v5 2/4] riscv/barrier: Define RISCV_FULL_BARRIER Eric Chan
2024-02-13 22:39 ` [PATCH v5 3/4] riscv/barrier: Consolidate fence definitions Eric Chan
2024-02-13 22:40 ` Eric Chan [this message]
2024-02-16 21:05 ` [PATCH v5 4/4] riscv/barrier: Resolve checkpatch.pl error Andrea Parri
2024-02-17 13:07 ` Eric Chan
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