From: Yang Xiwen via B4 Relay <devnull+forbidden405.outlook.com@kernel.org>
To: Wei Xu <xuwei5@hisilicon.com>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Jiancheng Xue <xuejiancheng@hisilicon.com>,
Alex Elder <elder@linaro.org>,
Peter Griffin <peter.griffin@linaro.org>
Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Yang Xiwen <forbidden405@outlook.com>
Subject: [PATCH v2 2/3] arm64: dts: hi3798cv200: add GICH, GICV register space and irq
Date: Sun, 18 Feb 2024 20:02:51 +0800 [thread overview]
Message-ID: <20240218-cache-v2-2-1fd919e2bd3e@outlook.com> (raw)
In-Reply-To: <20240218-cache-v2-0-1fd919e2bd3e@outlook.com>
From: Yang Xiwen <forbidden405@outlook.com>
This is needed by KVM to make use of VGIC code. Just like regular
GIC-400, PPI #9 is the hypervisor maintenance interrupt. It has been
verified.
Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
---
arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
index d01023401d7e..fc64d2fa99eb 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
@@ -58,7 +58,11 @@ cpu@3 {
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */
- <0x0 0xf1002000 0x0 0x2000>; /* GICC */
+ <0x0 0xf1002000 0x0 0x2000>, /* GICC */
+ <0x0 0xf1004000 0x0 0x2000>, /* GICH */
+ <0x0 0xf1006000 0x0 0x2000>; /* GICV */
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_HIGH)>;
#address-cells = <0>;
#interrupt-cells = <3>;
interrupt-controller;
--
2.43.0
next prev parent reply other threads:[~2024-02-18 12:03 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-18 12:02 [PATCH v2 0/3] arm64: dts: hi3798cv200: fix GICR size, add cache info, maintenance irq and GICH, GICV spaces Yang Xiwen via B4 Relay
2024-02-18 12:02 ` [PATCH v2 1/3] arm64: dts: hi3798cv200: fix the size of GICR Yang Xiwen via B4 Relay
2024-02-18 12:02 ` Yang Xiwen via B4 Relay [this message]
2024-02-18 12:02 ` [PATCH v2 3/3] arm64: dts: hi3798cv200: add cache info Yang Xiwen via B4 Relay
2024-02-19 7:20 ` Krzysztof Kozlowski
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